DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/13/2024 and 01/02/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I and Species A4, B3, C3, D3, and E5 (claims 1-16) in the reply filed on 01/26/2026 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3, 5, and 7 are rejected under 35 U.S.C. 102(a)(1)(a)(2) as being anticipated by Liu (US Publication 20210074709).
Regarding independent claim 1, Liu teaches an integrated circuit comprising:
a first circuit die (fig. 4, 410) having a first metal stack (420), wherein the first circuit die corresponds to a primary thermal source of the integrated circuit (paragraphs 0036 and 0051);
a second circuit die (432) having a second metal stack (430) that is connected to the first metal stack of the first circuit die (fig. 4); and
one or more connection elements (426 and 428) provided to the second circuit die, wherein the one or more connection elements configure the second circuit die for connection to at least one of a package substrate or an additional die (paragraph 0055, “contacts 428 and surrounding dielectrics in bonding layer 426 can be used for hybrid bonding”).
Regarding dependent claim 2, Liu teaches the integrated circuit of claim 1, wherein the first circuit die includes logic transistors (fig. 4, 418) that are manufactured in isolation (paragraph 0051) and contains a majority of all logic transistors of the integrated circuit, and the second circuit die contains a majority of static random access memory and analog devices of the integrated circuit (paragraph 0058).
Regarding dependent claim 3, Liu teaches the integrated circuit of claim 2, wherein the second circuit die corresponds to a pair node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the pair node (paragraph 0036).
Regarding dependent claim 5, Liu teaches the integrated circuit of claim 1, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using through silicon vias (paragraph 0035).
Regarding dependent claim 7, Liu teaches the integrated circuit of claim 1, wherein the one or more connection elements include one or more routing layers (fig. 4, 426) in the second circuit die configured for connection to the additional die using direct bonding (paragraph 0056).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Or-Bach et al. (US Publication 20220013485).
Regarding dependent claim 6, Liu teaches the integrated circuit of claim 1.
Liu does not teach wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using nano through silicon vias.
Or-Bach teaches wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using nano through silicon vias (paragraph 0222).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit of Liu and the nano through silicon vias of Or-Bach in order to assure the desired electrical and physical contact (Or-Bach paragraph 0222).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Arabi et al. (US Publication 20060052970).
Regarding dependent claim 8, Liu teaches the integrated circuit of claim 1.
Liu does not teach wherein the configuration of the second circuit die for connection configures the first circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device containing the integrated circuit.
Arabi teaches wherein the configuration of the second circuit die (fig. 1, 110) for connection configures the first circuit die (140) for positioning closer than the second circuit die to a cooling solution (130) of a semiconductor device containing the integrated circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit of Liu and the cooling solution of Arabi in order to conduct heat generated by IC 110 away from package 120 (Arabi paragraph 0016).
Claims 4, 9-14, and 16 rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Dubey et al. (US Publication 20200076424).
Regarding independent claim 9, Liu teaches a semiconductor device (fig. 4, 400) comprising:
an integrated circuit that includes a first circuit die (410) connected to a second circuit die (432), wherein the first circuit die corresponds to a primary thermal source of the integrated circuit (paragraphs 0036 and 0051).
Liu does not teach an additional die; and one or more connection elements connecting the second circuit die to the additional die.
Dubey teaches an additional die (fig. 1, 54); and
one or more connection elements (52) connecting the second circuit die (34) to the additional die.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Liu and the additional die of Dubey in order to include one or more subsystems for a field programmable gate array (Dubey paragraph 0019).
Regarding dependent claim 10, further teaches the semiconductor device of claim 9, further comprising:
a heat spreader positioned above the first circuit die.
Regarding dependent claim 11, teaches the semiconductor device of claim 10, further comprising:
thermal interface material positioned between the first circuit die and the heat spreader.
Regarding dependent claim 12, Liu further teaches the semiconductor device of claim 9, wherein the first circuit die includes logic transistors (fig. 4, 418) that are manufactured in isolation (paragraph 0051) and contains a majority of all logic transistors of the integrated circuit, the second circuit die contains a majority of static random access memory and analog devices of the integrated circuit (paragraph 0058), and the first circuit die is constructed according to a more advanced technology process compared to the second circuit die (paragraph 0036).
Regarding dependent claims 4 and 13, Dubey further teaches the integrated circuit of claim 1/semiconductor device of claim 9, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using microbumps (paragraph 0066).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit/semiconductor device of Liu and the microbumps of Dubey per the reason(s) stated above in claim 9.
Regarding dependent claim 14, Liu further teaches the semiconductor device of claim 9, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using through silicon vias (paragraph 0035).
Regarding dependent claim 16, Liu further teaches the semiconductor device of claim 9, wherein the one or more connection elements include one or more routing layers (426) in the second circuit die connected to the additional die using direct bonding (paragraph 0056).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Dubey as applied to claim 9 above, and further in view of Or-Bach.
Regarding dependent claim 15, Liu teaches the semiconductor device of claim 9.
Liu does not teach wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using nano through silicon vias.
Or-Bach teaches wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using nano through silicon vias (paragraph 0222).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine semiconductor device of Liu and the nano through silicon vias of Or-Bach in order to assure the desired electrical and physical contact (Or-Bach paragraph 0222).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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