DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III, as presented in Fig. 6, in the reply filed on 5 January 2026 is acknowledged.
Claims 6, 13, & 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5 January 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “fuse value distribution path” recited in Claims 2, 9, & 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is unclear. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LOGIC DIE PAIRED WITH MEMORY DIE HAVING FUSES AND PHASE LOCK LOOPS DISPOSED IN MEMORY DIE
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 5, 7 – 12, 14 – 18, & 20 and their respective dependent claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Lin. 4 – 5 recite the limitation “the one or more fuses identify the circuit die”. However, this limitation is unclear because what the one or more fuses identify the circuit die as is unclear. For the purposes of examination, this limitation will be interpreted as “the one or more fuses identify the circuit die as different from the one or more additional circuit die”.
Regarding Claim 2,
Lin. 1 – 2 recite the term “fuse value distribution paths” which has no known ordinary meaning and is not defined in the instant application. Thus, the term is indefinite because the specification does not clearly redefine the term. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, or in lieu thereof, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). For the purposes of examination, this term will be interpreted as “fusible paths” where “fusible” is used by Applicant in Par. 59 of the instant application.
Regarding Claim 3,
Lin. 2 recites the limitation “manufactured in isolation”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “manufactured separately from the one or more additional circuit die”.
Lin. 2 – 3 recite the limitation “constructed according to a more advanced technology process”. However, this language is ambiguous, rendering the claim indefinite. Specifically, it is unclear as to what the metric is for determining one process to be a more advanced technology process than another process. Reasonable guesses for this metric such as cost, the number of masks used, the number of steps required, and the time required all appear to fall short. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a different process”.
Regarding Claim 4,
Lin. 1 – 2 recite the limitation “a majority of all logic transistors of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 1—upon which this claim depends—recites an open-ended composition of the integrated circuit (i.e. “An integrated circuit comprising”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all logic transistors of the integrated circuit” includes or excludes logic transistors of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed logic transistors of the integrated circuit”.
Lin. 2 – 3 recite the limitation “a majority of all static random access memory and analog devices of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 1—upon which this claim depends—recites an open-ended composition of the integrated circuit (i.e. “An integrated circuit comprising”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all static random access memory and analog devices of the integrated circuit” includes or excludes static random access memory and analog devices of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed static random access memory and analog devices of the integrated circuit”.
Regarding Claim 5,
Lin. 2 – 3 recite the limitation “high speed, standalone testing”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “testing”.
Lin. 2 recites the limitation “phase lock loops”. However, this limitation is unclear with regard to what the phase lock loops may belong and/or may not belong, rendering the claim indefinite. For the purposes of examination, this limitation will be interpreted as “all phase lock loops of the integrated circuit”.
Lin. 2 recites—including the interpretation above—"a majority of all phase lock loops of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 1—upon which this claim depends—recites an open-ended composition of the integrated circuit (i.e. “An integrated circuit comprising”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all phase lock loops of the integrated circuit” includes or excludes phase lock loops of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed phase lock loops of the integrated circuit”.
Regarding Claim 7,
Lin. 1 – 2 recite the limitation “constructed according to a chip on wafer process using the circuit die as a base wafer”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a process using the circuit die as a base”, as supported by the elected species in Fig. 6 of the instant application.
Regarding Claim 8,
Lin. 6 recites the limitation “the one or more fuses identify the circuit die”. However, this limitation is unclear because what the one or more fuses identify the circuit die as is unclear. For the purposes of examination, this limitation will be interpreted as “the one or more fuses identify the circuit die as different from the one or more additional circuit die”.
Regarding Claim 9,
Lin. 1 – 2 recite the term “fuse value distribution paths” which has no known ordinary meaning and is not defined in the instant application. Thus, the term is indefinite because the specification does not clearly redefine the term. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, or in lieu thereof, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). For the purposes of examination, this term will be interpreted as “fusible paths” where “fusible” is used by Applicant in Par. 59 of the instant application.
Regarding Claim 10,
Lin. 2 recites the limitation “manufactured in isolation”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “manufactured separately from the one or more additional circuit die”.
Lin. 2 – 3 recite the limitation “constructed according to a more advanced technology process”. However, this language is ambiguous, rendering the claim indefinite. Specifically, it is unclear as to what the metric is for determining one process to be a more advanced technology process than another process. Reasonable guesses for this metric such as cost, the number of masks used, the number of steps required, and the time required all appear to fall short. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a different process”.
Regarding Claim 11,
Lin. 1 – 2 recite the limitation “a majority of all logic transistors of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 8—upon which this claim depends—recites an open-ended composition of the integrated circuit (i.e. “an integrated circuit that includes”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all logic transistors of the integrated circuit” includes or excludes logic transistors of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed logic transistors of the integrated circuit”.
Lin. 2 – 3 recite the limitation “a majority of all static random access memory and analog devices of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 8—upon which this claim depends—recites an open-ended composition of the integrated circuit (e.g. “an integrated circuit comprising”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all static random access memory and analog devices of the integrated circuit” includes or excludes static random access memory and analog devices of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed static random access memory and analog devices of the integrated circuit”.
Regarding Claim 12,
Lin. 3 recites the limitation “high speed, standalone testing”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “testing”.
Lin. 2 recites the limitation “phase lock loops”. However, this limitation is unclear with regard to what the phase lock loops may belong and/or may not belong, rendering the claim indefinite. For the purposes of examination, this limitation will be interpreted as “all phase lock loops of the integrated circuit”.
Lin. 2 recites—including the interpretation above—"a majority of all phase lock loops of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as Claim 8—upon which this claim depends—recites an open-ended composition of the integrated circuit (i.e. “an integrated circuit that includes”). As the composition of the integrated circuit is open-ended, whether or not “a majority of all phase lock loops of the integrated circuit” includes or excludes phase lock loops of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed phase lock loops of the integrated circuit”.
Regarding Claim 14,
Lin. 1 – 2 recite the limitation “constructed according to a chip on wafer process using the circuit die as a base wafer”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a process using the circuit die as a base”, as supported by the elected species in Fig. 6 of the instant application.
Regarding Claim 15,
Lin. 4 recites the limitation “the one or more fuses identify the circuit die”. However, this limitation is unclear because what the one or more fuses identify the circuit die as is unclear. For the purposes of examination, this limitation will be interpreted as “the one or more fuses identify the circuit die as different from the one or more additional circuit die”.
Regarding Claim 16,
Lin. 1 – 2 recite the term “fuse value distribution paths” which has no known ordinary meaning and is not defined in the instant application. Thus, the term is indefinite because the specification does not clearly redefine the term. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, or in lieu thereof, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). For the purposes of examination, this term will be interpreted as “fusible paths” where “fusible” is used by Applicant in Par. 59 of the instant application.
Regarding Claim 17,
Lin. 2 recites the limitation “manufactured in isolation”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “manufactured separately from the one or more additional circuit die”.
Lin. 2 – 3 recite the limitation “constructed according to a more advanced technology process”. However, this language is ambiguous, rendering the claim indefinite. Specifically, it is unclear as to what the metric is for determining one process to be a more advanced technology process than another process. Reasonable guesses for this metric such as cost, the number of masks used, the number of steps required, and the time required all appear to fall short. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a different process”.
Regarding Claim 18,
Lin. 1 – 2 recite the limitation “a majority of all logic transistors of an integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as neither this claim nor Claim 15—upon which this claim depends—recites of what the integrated circuit is comprised and/or consists. As the composition of the integrated circuit is not disclosed, whether or not “a majority of all logic transistors of an integrated circuit” includes or excludes logic transistors of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed logic transistors of an integrated circuit”.
Lin. 2 – 3 recite the limitation “a majority of all static random access memory and analog devices of the integrated circuit”. However, this limitation is unclear, rendering the claim indefinite, as neither this claim nor Claim 15—upon which this claim depends—recites of what the integrated circuit is comprised and/or consists. As the composition of the integrated circuit is not disclosed, whether or not “a majority of all static random access memory and analog devices of the integrated circuit” includes or excludes static random access memory and analog devices of components of the integrated circuit not explicitly disclosed is unclear. For the purposes of examination, this limitation will be interpreted as “a majority of all disclosed static random access memory and analog devices of the integrated circuit”.
Regarding Claim 20,
Lin. 2 – 3 recite the limitation “constructed according to a chip on wafer process using the circuit die as a base wafer”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “constructed according to a process using the circuit die as a base”, as supported by the elected species in Fig. 6 of the instant application.
Examiner’s Note
A number of the limitations in the following claims are product-by-process limitations or functional limitations. For the sake of compact prosecution, the Examiner respectfully notes the following:
It has been well established that “even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The
patentability of a product does not depend on its method of production. If the product in the
product-by-process claim is the same as or obvious from a product of the prior art, the claim is
unpatentable even though the prior product was made by a different process." In re Thorpe, 777
F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113 I.
Furthermore, it has been well established that the manner of operating a device does not
differentiate a device claim from a prior art device. "[A]pparatus claims cover what a device is,
not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15
USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation
with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches
all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. &
Inter. 1987), MPEP 2114 II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 - 2, 7 – 9, 14 – 16, & 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by OH (US 20140014958 A1).
Regarding Claim 1,
OH discloses:
An integrated circuit (Fig. 5: 30 & 120) comprising:
a circuit die (Fig. 5: 30);
one or more additional circuit die (Fig. 5: 120) connected to the circuit die (30); and
one or more fuses (Fig. 4 & 5: F) positioned in the one or more additional circuit die (120),
wherein the one or more fuses (F) identify the circuit die (30) as different from the one or more additional circuit die (120).
(Fig. 5: the F identify 30 as different from 120 by process of elimination. That is, 30 does not comprise F, and 120 does comprise F.)
Regarding Claim 2,
OH discloses:
The integrated circuit of claim 1, wherein
the one or more fuses (F) have fusible paths provisioned to the circuit die (30).
(As seen in Fig. 5)
Regarding Claim 7,
OH discloses:
The integrated circuit of claim 1, wherein
the integrated circuit (30 & 120) is constructed according to a process using the circuit die (30) as a base.
(By whatever process 30 & 120 of OH is constructed, according to Fig. 5, 30 is used as a base for 120.)
Regarding Claim 8,
OH discloses:
A semiconductor device (Fig. 5: all components), comprising: an integrated circuit (Fig. 5: 30 & 120) that includes:
a circuit die (Fig. 5: 30);
one or more additional circuit die (Fig. 5: 120) connected to the circuit die (30); and
one or more fuses (Fig. 4 & 5: F) positioned in the one or more additional circuit die (120), wherein
the one or more fuses (F) identify the circuit die (30) as different from the one or more additional circuit die (120); and
(Fig. 5: the F identify 30 as different from 120 by process of elimination. That is, 30 does not comprise F, and 120 does comprise F.)
an additional die (Fig. 5: 110) connected to the one or more additional circuit die (120).
Regarding Claim 9,
OH discloses:
The semiconductor device of claim 8, wherein
the one or more fuses (F) have fusible paths provisioned to the circuit die (30).
(As seen in Fig. 5)
Regarding Claim 14,
OH discloses:
The semiconductor device of claim 8, wherein
the integrated circuit (30 & 120) is constructed according to a process using the circuit die (30) as a base.
(By whatever process 30 & 120 of OH is constructed, according to Fig. 5, 30 is used as a base for 120.)
Regarding Claim 15,
OH discloses:
A method, comprising:
providing a circuit die (Fig. 5: 30);
providing one or more additional circuit die (Fig. 5: 120) having one or more fuses (Fig. 4 & 5: F) positioned therein,
wherein the one or more fuses (F) identify the circuit die (30) as different from the one or more additional circuit die (120); and
(Fig. 5: the F identify 30 as different from 120 by process of elimination. That is, 30 does not comprise F, and 120 does comprise F.)
connecting the one or more additional circuit die (120) to the circuit die (30).
(As seen in Fig. 5)
Regarding Claim 16,
OH discloses:
The method of claim 15, wherein
the one or more fuses (F) have fusible paths provisioned to the circuit die (30).
(As seen in Fig. 5)
Regarding Claim 20,
OH discloses:
The method of claim 15, wherein
the circuit die (30) and the one or more additional circuit die (120) are constructed according to a process using the circuit die (30) as a base.
(By whatever process 30 and 120 of OH are constructed, according to Fig. 5, 30 is used as a base for 120.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 10, & 17 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of KATO (US 20020140107 A1).
Regarding Claim 3,
OH discloses:
The integrated circuit of claim 1, wherein
the circuit die (30) includes logic transistors…and
(Par. 56 teaches 30 may be a “system chip”, which may be a “central processing unit”, as per Par. 5, which inherently comprises logic transistors.)
the circuit die (30) is constructed according to a different process compared to the one or more additional circuit die (120).
(As 30 may be a “central processing unit” and 120 may be a “memory chip”, as per Par. 45, 30 and 120 are different in design. Therefore, 30 is necessarily constructed according to a different process compared to 120.)
OH does not disclose:
wherein the logic transistors are manufactured separately from the one or more additional circuit die.
KATO discloses:
wherein the logic transistors (Fig. 1 shows a circuit die 12A, which is a “logic chip”, as per Par. 187, such as a central processing unit, which inherently comprises logic transistors) are manufactured separately from the one or more additional circuit die (Fig. 1: 11A).
(Par. 188 teaches the merits of manufacturing 12A—and thus the logic transistors included therein—separately from 11A.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KATO to enable the circuit die—and thus the logic transistors included therein—to be manufactured separately from the one or more additional circuit die in OH according to the teachings of KATO for the further advantage of manufacturing the associated integrated circuit with a better yield, at a lower cost, and in a shorter amount of time compared to when the circuit die—and thus the logic transistors included therein—are not manufactured separately from the one or more additional circuit die (KATO Par. 188).
Regarding Claim 10,
OH discloses:
The semiconductor device of claim 8, wherein
the circuit die (30) includes logic transistors…and
(Par. 56 teaches 30 may be a “system chip”, which may be a “central processing unit”, as per Par. 5, which inherently comprises logic transistors.)
the circuit die (30) is constructed according to a different process compared to the one or more additional circuit die (120).
(As 30 may be a “central processing unit” and 120 may be a “memory chip”, as per Par. 45, 30 and 120 are different in design. Therefore, 30 is necessarily constructed according to a different process compared to 120.)
OH does not disclose:
wherein the logic transistors are manufactured separately from the one or more additional circuit die.
KATO discloses:
wherein the logic transistors (Fig. 1 shows a circuit die 12A, which is a “logic chip”, as per Par. 187, such as a central processing unit, which inherently comprises logic transistors) are manufactured separately from the one or more additional circuit die (Fig. 1: 11A).
(Par. 188 teaches the merits of manufacturing 12A—and thus the logic transistors included therein—separately from 11A.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KATO to enable the circuit die—and thus the logic transistors included therein—to be manufactured separately from the one or more additional circuit die in OH according to the teachings of KATO for the further advantage of manufacturing the associated integrated circuit with a better yield, at a lower cost, and in a shorter amount of time compared to when the circuit die—and thus the logic transistors included therein—are not manufactured separately from the one or more additional circuit die (KATO Par. 188).
Regarding Claim 17,
OH discloses:
The method of claim 15, wherein
the circuit die (30) includes logic transistors…and
(Par. 56 teaches 30 may be a “system chip”, which may be a “central processing unit”, as per Par. 5, which inherently comprises logic transistors.)
the circuit die (30) is constructed according to a different process compared to the one or more additional circuit die (120).
(As 30 may be a “central processing unit” and 120 may be a “memory chip”, as per Par. 45, 30 and 120 are different in design. Therefore, 30 is necessarily constructed according to a different process compared to 120.)
OH does not disclose:
wherein the logic transistors are manufactured separately from the one or more additional circuit die.
KATO discloses:
wherein the logic transistors (Fig. 1 shows a circuit die 12A, which is a “logic chip”, as per Par. 187, such as a central processing unit, which inherently comprises logic transistors) are manufactured separately from the one or more additional circuit die (Fig. 1: 11A).
(Par. 188 teaches the merits of manufacturing 12A—and thus the logic transistors included therein—separately from 11A.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KATO to enable the circuit die—and thus the logic transistors included therein—to be manufactured separately from the one or more additional circuit die in OH according to the teachings of KATO for the further advantage of manufacturing the associated integrated circuit with a better yield, at a lower cost, and in a shorter amount of time compared to when the circuit die—and thus the logic transistors included therein—are not manufactured separately from the one or more additional circuit die (KATO Par. 188).
Claims 4, 11, & 18 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of MAJHI (US 20230022167 A1).
Regarding Claim 4,
OH discloses:
The integrated circuit of claim 1, wherein
the one or more additional circuit die (120) contains a majority of all disclosed…memory and analog devices of the integrated circuit (30 & 120).
(The only memory devices of 30 & 120 disclosed by OH are the one or more additional circuit die 120, per se, Par. 45. As such, 120 contains a majority of all disclosed memory devices of 30 & 120.)
(The only analog devices of 30 & 120 disclosed by OH are the one or more fuses, all of which 120 contains, as per Fig. 5. As such, 120 contains a majority of all disclosed analog devices of 30 & 120.)
OH does not disclose:
the circuit die contains a majority of all disclosed logic transistors of the integrated circuit
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable the circuit die to contain a majority of all disclosed logic transistors of the integrated circuit, as one of ordinary skill in the art would recognize the only disclosed components of the integrated circuit (OH Fig. 5: 30 & 120) for this claim that would contain an appreciable number of logic transistors are the circuit die, which may be a “central processing unit” (OH Fig. 5: 30; Par. 5 & 56), and the one or more additional circuit die, which may be a “memory chip” (OH Fig. 5: 120; Par. 45) where central processing units are known in the art to contain a much larger number of logic transistors compared to memory chips. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the circuit die to contain a majority of all disclosed logic transistors of the integrated circuit.
OH does not disclose:
the memory devices are static random access memory devices
MAJHI discloses:
the memory devices (Fig. 4A: 106-1) are static random access memory devices (Par. 43, where 106-1 of Fig. 4A may be the same as 106-1 of Fig. 3, as per Par. 45.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of MAJHI to enable the memory devices to be static random access memory devices in OH according to the teachings of MAJHI, as OH discloses said memory devices (OH Fig. 5: 120) for the embodiment in question (OH Fig. 5: 30 & 120) but does not disclose the type of memory devices, specifically. Additionally, OH discloses the memory (OH Fig. 7: 1330) of a related embodiment (OH Fig. 7) may include “a volatile memory device” (OH Par. 63) but, similarly, does not disclose what type of volatile memory device, specifically. Therefore, a person having ordinary skill in the art would look to the prior art for a specific type of memory device, or at least a specific type of volatile memory device, recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the static random access memory devices of MAJHI meet these criteria, as the memory devices of both OH and MAJHI are similar in that both provide memory for the circuit die (OH Fig. 5: 30 & MAJHI Fig. 4A: 104) of a similar integrated circuit device (OH Fig. 5: 30 & 120; MAJHI Fig. 4A: 140 & 106-1).
Regarding Claim 11,
OH discloses:
The semiconductor device of claim 8, wherein
the one or more additional circuit die (120) contains a majority of all disclosed…memory and analog devices of the integrated circuit (30 & 120).
(The only memory devices of 30 & 120 disclosed by OH are the one or more additional circuit die 120, per se, Par. 45. As such, 120 contains a majority of all disclosed memory devices of 30 & 120.)
(The only analog devices of 30 & 120 disclosed by OH are the one or more fuses, all of which 120 contains, as per Fig. 5. As such, 120 contains a majority of all disclosed analog devices of 30 & 120.)
OH does not disclose:
the circuit die contains a majority of all disclosed logic transistors of the integrated circuit
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable the circuit die to contain a majority of all disclosed logic transistors of the integrated circuit, as one of ordinary skill in the art would recognize the only disclosed components of the integrated circuit (OH Fig. 5: 30 & 120) for this claim that would contain an appreciable number of logic transistors are the circuit die, which may be a “central processing unit” (OH Fig. 5: 30; Par. 5 & 56), and the one or more additional circuit die, which may be a “memory chip” (OH Fig. 5: 120; Par. 45) where central processing units are known in the art to contain a much larger number of logic transistors compared to memory chips. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the circuit die to contain a majority of all disclosed logic transistors of the integrated circuit.
OH does not disclose:
the memory devices are static random access memory devices
MAJHI discloses:
the memory devices (Fig. 4A: 106-1) are static random access memory devices (Par. 43, where 106-1 of Fig. 4A may be the same as 106-1 of Fig. 3, as per Par. 45.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of MAJHI to enable the memory devices to be static random access memory devices in OH according to the teachings of MAJHI, as OH discloses said memory devices (OH Fig. 5: 120) for the embodiment in question (OH Fig. 5: all components) but does not disclose the type of memory devices, specifically. Additionally, OH discloses the memory (OH Fig. 7: 1330) of a related embodiment (OH Fig. 7) may include “a volatile memory device” (OH Par. 63) but, similarly, does not disclose what type of volatile memory device, specifically. Therefore, a person having ordinary skill in the art would look to the prior art for a specific type of memory device, or at least a specific type of volatile memory device, recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the static random access memory devices of MAJHI meet these criteria, as the memory devices of both OH and MAJHI are similar in that both provide memory for the circuit die (OH Fig. 5: 30 & MAJHI Fig. 4A: 104) of a similar integrated circuit device (OH Fig. 5: 30 & 120; MAJHI Fig. 4A: 140 & 106-1).
Regarding Claim 18,
OH discloses:
The method of claim 15, wherein
the one or more additional circuit die (120) contains a majority of all disclosed…memory and analog devices of an integrated circuit (30 & 120).
(The only memory devices of 30 & 120 disclosed by OH are the one or more additional circuit die 120, per se, Par. 45. As such, 120 contains a majority of all disclosed memory devices of 30 & 120.)
(The only analog devices of 30 & 120 disclosed by OH are the one or more fuses, all of which 120 contains, as per Fig. 5. As such, 120 contains a majority of all disclosed analog devices of 30 & 120.)
OH does not disclose:
the circuit die contains a majority of all disclosed logic transistors of an integrated circuit
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable the circuit die to contain a majority of all disclosed logic transistors of an integrated circuit, as one of ordinary skill in the art would recognize the only disclosed components of the integrated circuit (OH Fig. 5: 30 & 120) for this claim that would contain an appreciable number of logic transistors are the circuit die, which may be a “central processing unit” (OH Fig. 5: 30; Par. 5 & 56), and the one or more additional circuit die, which may be a “memory chip” (OH Fig. 5: 120; Par. 45) where central processing units are known in the art to contain a much larger number of logic transistors compared to memory chips. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the circuit die to contain a majority of all disclosed logic transistors of an integrated circuit.
OH does not disclose:
the memory devices are static random access memory devices
MAJHI discloses:
the memory devices (Fig. 4A: 106-1) are static random access memory devices (Par. 43, where 106-1 of Fig. 4A may be the same as 106-1 of Fig. 3, as per Par. 45.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of MAJHI to enable the memory devices to be static random access memory devices in OH according to the teachings of MAJHI, as OH discloses said memory devices (OH Fig. 5: 120) for the embodiment in question (OH Fig. 5: 30 & 120) but does not disclose the type of memory devices, specifically. Additionally, OH discloses the memory (OH Fig. 7: 1330) of a related embodiment (OH Fig. 7) may include “a volatile memory device” (OH Par. 63) but, similarly, does not disclose what type of volatile memory device, specifically. Therefore, a person having ordinary skill in the art would look to the prior art for a specific type of memory device, or at least a specific type of volatile memory device, recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the static random access memory devices of MAJHI meet these criteria, as the memory devices of both OH and MAJHI are similar in that both provide memory for the circuit die (OH Fig. 5: 30 & MAJHI Fig. 4A: 104) of a similar integrated circuit device (OH Fig. 5: 30 & 120; MAJHI Fig. 4A: 140 & 106-1).
Claims 5 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of KELLY (US 20050248036 A1).
Regarding Claim 5,
OH does not disclose:
The integrated circuit of claim 1, wherein
the one or more additional circuit die contains a majority of all disclosed phase lock loops of the integrated circuit that generate one or more clock signals useful for testing of the integrated circuit.
KELLY discloses:
the one or more additional circuit die (Fig. 4A: 202B-1, which is a memory device; Par. 21) contains a majority of all disclosed phase lock loops (Par. 21 discloses phases lock loops in 202B-1 but does not disclose phase lock loops in circuit die 202A-1, which may be a “processor”, or elsewhere in the integrated circuit: 202A-1 & 202B-1) of the integrated circuit (202A-1 & 202B-1).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KELLY to enable the integrated circuit to comprise phase lock loops in OH according to the teachings of KELLY, as OH fails to disclose said phase lock loops, which are a common and important component of such integrated circuit devices (KELLY Par. 23). Therefore, a person having ordinary skill in the art would look to the prior art for a similar integrated circuit device recognized for its suitability and intended purpose, comprising said phase lock loops (MPEP 2144.07). Further still, the integrated circuit device of KELLY meets these criteria, as the integrated circuit devices of both OH and KELLY are similar in that both are multi-chip packages (OH Fig. 5: 30 & 120 and KELLY Fig. 4A: 202A-1 & 202B-1) comprising a circuit die (OH Fig. 5: 30 and KELLY Fig. 4A: 202A-1), which may be a logic chip (OH Par. 5 & 56 and KELLY Par. 21), and one or more additional circuit die (OH Fig. 5: 120 and KELLY Fig. 4A: 202B-1), which may be memory devices (OH Par. 45 and KELLY Par. 21) connected to the associated logic chip.
Additionally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KELLY to enable the one or more additional circuit die to contain a majority of all disclosed phase lock loops of the integrated circuit in OH according to the teachings of KELLY for the further advantage of optimizing the circuit die around its speed and performance requirements separate from optimizing the one or more additional circuit die around its speed and performance requirements, which yields a reduction in cost compared to optimizing a single die comprising the functionality of both the circuit die and the one or more additional circuit die (KELLY Par. 24).
KELLY does not disclose:
wherein the phase lock loops generate one or more clock signals useful for testing of the integrated circuit.
Nevertheless, this limitation regards the manner in which the claimed phase lock loops are intended to be employed, and a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim (MPEP 2114 II). Hence, the requirement that “the phase lock loops generate one or more clock signals useful for testing of the integrated circuit” does not patentably distinguish Applicant’s claimed integrated circuit device from the known integrated circuit device of OH in view of KELLY, as OH in view of KELLY teaches all the structural limitations of this claim: “The integrated circuit of claim 1, wherein the one or more additional circuit die contains a majority of all disclosed phase lock loops of the integrated circuit”.
Regarding Claim 12,
OH does not disclose:
The semiconductor device of claim 8, wherein
the one or more additional circuit die contains a majority of all disclosed phase lock loops of the integrated circuit that generate one or more clock signals useful for testing of the integrated circuit.
KELLY discloses:
the one or more additional circuit die (Fig. 4A: 202B-1, which is a memory device; Par. 21) contains a majority of all disclosed phase lock loops (Par. 21 discloses phases lock loops in 202B-1 but does not disclose phase lock loops in circuit die 202A-1, which may be a “processor”, or elsewhere in the integrated circuit: 202A-1 & 202B-1) of the integrated circuit (202A-1 & 202B-1).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KELLY to enable the integrated circuit to comprise phase lock loops in OH according to the teachings of KELLY, as OH fails to disclose said phase lock loops, which are a common and important component of such integrated circuit devices (KELLY Par. 23). Therefore, a person having ordinary skill in the art would look to the prior art for a similar integrated circuit device recognized for its suitability and intended purpose, comprising said phase lock loops (MPEP 2144.07). Further still, the integrated circuit device of KELLY meets these criteria, as the integrated circuit devices of both OH and KELLY are similar in that both are multi-chip packages (OH Fig. 5: 30 & 120 and KELLY Fig. 4A: 202A-1 & 202B-1) comprising a circuit die (OH Fig. 5: 30 and KELLY Fig. 4A: 202A-1), which may be a logic chip (OH Par. 5 & 56 and KELLY Par. 21), and one or more additional circuit die (OH Fig. 5: 120 and KELLY Fig. 4A: 202B-1), which may be memory devices (OH Par. 45 and KELLY Par. 21) connected to the associated logic chip.
Additionally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of KELLY to enable the one or more additional circuit die to contain a majority of all disclosed phase lock loops of the integrated circuit in OH according to the teachings of KELLY for the further advantage of optimizing the circuit die around its speed and performance requirements separate from optimizing the one or more additional circuit die around its speed and performance requirements, which yields a reduction in cost compared to optimizing a single die comprising the functionality of both the circuit die and the one or more additional circuit die (KELLY Par. 24).
KELLY does not disclose:
wherein the phase lock loops generate one or more clock signals useful for testing of the integrated circuit.
Nevertheless, this limitation regards the manner in which the claimed phase lock loops are intended to be employed, and a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim (MPEP 2114 II). Hence, the requirement that “the phase lock loops generate one or more clock signals useful for testing of the integrated circuit” does not patentably distinguish Applicant’s claimed integrated circuit device from the known integrated circuit device of OH in view of KELLY, as OH in view of KELLY teaches all the structural limitations of this claim: “The integrated circuit of claim 1, wherein the one or more additional circuit die contains a majority of all disclosed phase lock loops of the integrated circuit”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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