Prosecution Insights
Last updated: April 19, 2026
Application No. 18/474,201

OPTICAL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Sep 25, 2023
Examiner
SRINIVASAN, SESHA SAIRAMAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tong Hsing Electronic Industries Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
3y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
19 granted / 28 resolved
At TC average
Strong +53% interview lift
Without
With
+52.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
63 currently pending
Career history
91
Total Applications
across all art units

Statute-Specific Performance

§103
71.4%
+31.4% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
7.1%
-32.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 28 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Invention 1, direct to Claims 1-9 in the reply filed 03/06/2026 is acknowledged and is under consideration. Response to Amendment The amendment with respect to claims 1-9 filed on 03/06/2026 have been fully c onsidered for examination based on their merits. The non-elected Claims 10-17 are withdrawn by the Applicant. Response to Arguments Applicant elected Claims 1-9 ( without traverse ) are considered and entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , and 3 -9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by, or alternatively under 35 U.S.C. 103 as obvious over Guo Xiong Wu et al, (hereinafter WU), US 20180003927 A1. Regarding Claim 1 , WU teaches an optical package structure (Fig. 2, 40, optoelectronic module) , comprising: an optical element (Fig. 7, 112, optoelectronic module wafer, [0042]) ; a bonding structural member (annotated Figure 7) being bonded to a surface (annotated Figure 7) of the optical element (Fig. 7, 112, optoelectronic module wafer, [0042]) , wherein the bonding structural member (annotated Figure 7) includes a first bonding layer (Fig. 7, 128, first micro-spacers) , a light-absorption layer (Fig. 7, 124, second optical element layer, [0040]) , and a second bonding layer (Fig. 7, 130, second micro-spacers) , the first bonding layer (Fig. 7, 128, first micro-spacers) and the second bonding layer (Fig. 7, 130, second micro-spacers) are made of an opaque material ( the micro-spacers can be composed, for example, of an adhesive material, In some instances, the first and second micro-spacers are formed of a curable materials, [0007] ; in some implementations, it may be desirable to encapsulate the side edges of the optical elements and the micro-spacers, for example with an opaque or transparent material, [0061] ) , and the light-absorption layer (Fig. 7, 124, second optical element layer, [0040]) is disposed between the first bonding layer (Fig. 7, 128, first micro-spacers) and the second bonding layer (Fig. 7, 130, second micro-spacers) ; and a light transmittable member (Fig. 7, 122, first optical element layer, [0034]) being bonded (annotated Figure 7) to the bonding structural member (annotated Figure 7) and spaced apart (annotated Figure 7, [0007]) from the optical element (Fig. 7, 112, optoelectronic module wafer, [0042]) , wherein the light-absorption layer (Fig. 7, 124, second optical element layer, [0040]) is configured to absorb light (Fig. 7, 124, second optical element layer can be, for example, an IR absorber layer, a dielectric optical filter layer, or an optical interference filter layer, [0040]) emitted to the bonding structural member (annotated Figure 7) . Regarding Claim 3 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein a width (annotated Figure 7, thickness of the micro-spacers in a range of 20-50 microns, [0008]) of the second bonding layer (Fig. 7, 130, second micro-spacers, thickness of the micro-spacers in a range of 20-50 microns, [0008]) is smaller (annotated Figure 7) than a width (annotated Figure 7, thickness of the micro-spacers in a range of 20-50 microns, [0008]) of the first bonding layer (Fig. 7, 128, first micro-spacers, thickness of the micro-spacers in a range of 20-50 microns,) , so that the bonding structural member (annotated Figure 7) is stacked to have a stepped shape (annotated Figure 7) . Regarding Claim 4 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein the light-absorption layer (Figs. 1/7, 24/124, second optical element layer, [0040]) is selected from the group consisting of ink, an epoxy resin, and a photoresist material (polymers or epoxy materials, [0029]) . Regarding Claim 5 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein a height (annotated Figure 7) of the light-absorption layer (Fig. 7, 124, second optical element layer, [0040]) is 20% to 80% of a total height (annotated Figure 7) of the bonding structural member (annotated Figure 7) . Regarding Claim 6 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein an inner edge (annotated Figure 7) of the light-absorption layer (Fig. 7, 124, second optical element layer, [0040]) is arranged to be adjacent (annotated Figure 7; per https:/www.onelook.com/thesaurus, ‘adjacent’ meaning near, connected, adjoining, close etc.) to an inner edge (annotated Figure 7) of the first bonding layer (Fig. 7, 128, first micro-spacers) . Regarding Claim 7 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein the bonding structural member (Fig. 18, 220, multiple sub-assemblies; annotated Figure 18) further includes an additional light-absorption layer (annotated Figure 18) and a third bonding layer (annotated Figure 18) , the additional light-absorption layer (annotated Figure 18) is disposed on the second bonding layer (annotated Figure 18) , and the third bonding layer (annotated Figure 18) is disposed on the additional light-absorption layer (annotated Figure 18) . Regarding Claim 8 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein the optical element (Fig. 7, 112, optoelectronic module wafer, [0042]) is an image sensor (Fig. 7, 42, optoelectronic device, light sensor, [0031]) , the image sensor (Fig. 7, 42, optoelectronic device, light sensor, [0031]) includes a substrate (Fig. 7, 144, PCB wafer) and an image-sensing region (annotated Figure 7) disposed on a top surface of the substrate (Fig. 7, 144, PCB wafer) , and the image sensor (Fig. 7, 42, optoelectronic device, light sensor, [0031]) and the light transmittable member (Fig. 7, 122, first optical element layer) are spaced apart from each other (annotated Figure 7) ; wherein the first bonding layer (Fig. 7, 128, first micro-spacers) is bonded to the light transmittable member, and another side of the second bonding layer (Fig. 7, 130, second micro-spacers) is bonded to the substrate (Fig. 7, 144, PCB wafer) of the image sensor (Fig. 7, 42, optoelectronic device, light sensor, [0031]) . Regarding Claim 9 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1, wherein the optical element (Fig. 7, 112, optoelectronic module wafer, [0042]) is a display element (light emitter (LED, IRLED, OLED), [0031]) , the display element (light emitter (LED, IRLED, OLED), [0031]) includes a substrate (Fig. 7, 144, PCB wafer) and a display emitting region (annotated Figure 7) disposed on a top surface of the substrate (Fig. 7, 144, PCB wafer) , and the display element (light emitter (LED, IRLED, OLED), [0031]) and the light transmittable member (Fig. 7, 122, first optical element layer) are spaced apart from each other (annotated Figure 7) ; wherein the first bonding layer (Fig. 7, 128, first micro-spacers) is bonded to the light transmittable member (Fig. 7, 122, first optical element layer) , and another side of the second bonding layer (Fig. 7, 130, second micro-spacers) is bonded to the substrate (Fig. 7, 144, PCB wafer) of the display element (light emitter (LED, IRLED, OLED), [0031]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU, in view of Michael R. Feldman, (hereinafter FELDMAN), US 20100321564 A1. Regarding Claim 2 , WU teaches the optical package structure (Fig. 2, 40, optoelectronic module) according to claim 1. WU does not explicitly disclose the optical package structure, wherein a width of the light-absorption layer is smaller than a width of the first bonding layer, and a width of the second bonding layer is larger than the width of the light-absorption layer. FELDMAN teaches the optical package structure (Fig. 1D, 100, camera system) , wherein a width (annotated Figure 1D) of the light-absorption layer (Fig. 1D, S12, optical elements having power therein, e.g. separation, [0080]) is smaller (annotated Figure 1D) than a width (annotated Figure 1D) of the first bonding layer (Fig. 1D, 120, second substrate) , and a width (annotated Figure 1D) of the second bonding layer (Fig. 1D, 110, first substrate) is larger (annotated Figure 1D) than the width (annotated Figure 1D) of the light-absorption layer (Fig. 1D, S12, optical elements having power therein, e.g. separation, [0080]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified WU to incorporate the teachings of FELDMAN, such that the optical package structure, wherein a width of the light-absorption layer is smaller than a width of the first bonding layer, and a width of the second bonding layer is larger than the width of the light-absorption layer. The above arrangement is needed for the substrates to hold the optical elements, and may aide to both minimize the thickness of the device (e.g. camera system) and maximize the performance of the device (FELDMAN, [0085]) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20200373 3 41 A1 – Figure 1 STATEMENT OF RELEVANCE – Image sensor package comprising active pixel sensor region or APS region (110) spaced apart from the cover glass (400) by a bonding dam (200). US 20190154947 A1 – Figure 3 STATEMENT OF RELEVANCE – A vertical sectional view of a device, wherein a protective metal layer is arranged on the bonding object in each of the optical member fixing structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SESHA SAIRAMAN SRINIVASAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1389 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 7:30 AM -5:30 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine S. Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Sep 25, 2023
Application Filed
Apr 02, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
99%
With Interview (+52.9%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 28 resolved cases by this examiner. Grant probability derived from career allow rate.

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