DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 9-13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al (US Publication No. 2021/0118756) in view of Bean et al (US Publication No. 2022/0165705) and Bhagavat et al (US Publication No. 2019/0326273).
Regarding claim 1, Wan discloses a semiconductor package, comprising: a first die Fig 1, 110 or Fig 3B, 311 having a front side and a backside Fig 1 or Fig 3B; and a first supporter Fig 1, 121 or Fig 3B, 321c/321a disposed immediately under the first die Fig 1, 110 or Fig 3B, 311 and coupled to the first die Fig 1, 110 or Fig 3B, 311, wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die ¶0027 and 0031. Wan discloses all the limitations but silent on the specific connection between the die and the interposer. Whereas Bean discloses a first supporter Fig 1A, 104 disposed immediately under the first die Fig 1A, 140a/140b and thermally coupled to the first die ¶0038 Fig 1A, 140a/140b. Wan and Bean are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Wan and incorporate the teachings of Bean to improve device performance ¶0001-0003. Wan and Bean discloses all the limitations but silent on the material arrangement of the first supporter. Whereas Bhagavat discloses a supporter comprising a first material portion and a second material portion vertically stacking over the first material portion Fig 4 and Fig 14. Wan and Bhagavat are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Wan and incorporate the teachings of Bhagavat to improve device isolation.
Regarding claim 2, Wan discloses wherein the first supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon, and with the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die¶0027 and 0031 Fig 1 or Fig 3B.
Regarding claim 4, Wan discloses wherein the first supporter is composed of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, or silicon carbide¶ 0031.
Regarding claim 9, Wan and Bean discloses a plurality of second dies stacked over or disposed side-by-side with the first die; a structural member disposed side-by-side with the first die and the second dies; and a heat spreader disposed over the first die, the plurality of the second dies, and the structural member, wherein the structural member is thermally coupled with the first supporter and the heatsink, and the structural member possesses a thermal conductivity greater than the thermal conductivity of the first die Wan -Fig 1, 3A-5; Bean -Fig 1A-1D.
Regarding claim 10, Wan and Bean discloses wherein the structural member comprises (1) a plurality of interposers composed of a material with a thermal conductivity greater than that of silicon with through vias; (2) a spacer interconnect composed of a material with a thermal conductivity lower than that of silicon with or without a through via; (3) a vertical lead of the heat spreader; or a combination thereof Wan -Fig 1, 3A-5; Bean -Fig 1A-1D.
Regarding claim 11, Wan and Bean discloses wherein the heat spreader comprises a metal lid, an integrated heat spreader, a planar heatsink, a fin-type heatsink, a vapor chamber, a cold plate, a manifold, an interposer or a combination thereof, with the heat spreader thermally coupled to the structural member with or without a thermal interface material (TIM) having a thermal conductivity greater than that of silicon Wan -Fig 1, 3A-5; Bean -Fig 1A-1D.
Regarding claim 12, Wan and Bean discloses: a second supporter between the first die and one of the second dies, or between adjacent second dies, wherein the second supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon; and a through via in the second supporter Wan -Fig 1, 3A-5; Bean -Fig 1A-1D.
Regarding claim 13, Wan and Bean discloses a heat spreading layer or a thermal isolation layer in respective interconnect structure of the first supporter, the second supporter, the second dies, or a combination thereof Wan -Fig 1, 3A-5; Bean -Fig 1A-1D.
Regarding claim 15, Bean discloses wherein the backside of the first die is located in close proximity to the first supporter and the front side of the first die is farther away from the first supporter compared to the backside, and the semiconductor package further comprising: a plurality of second dies stacked over or disposed side-by-side with the first die; a second supporter between the first die and one of the second dies, or between adjacent second dies; a structural member disposed side-by-side with the first die and the second dies with the structural member having a thermal conductivity greater than the thermal conductivity of the first die; a heat spreader over the plurality of second dies and the first die with the heat spreader thermally coupled to the structural member; a carrier supporting the first die, the first supporter, the second dies, and the second supporter; and a flexible circuit interconnect electrically connecting the carrier or the first supporter to a circuit layer proximal to the heat spreader with the flexible circuit interconnect configured to provide power and signaling to one of the second dies or the front side of the first die Fig 1A-1D.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al (US Publication No. 2021/0118756) in view of Bean et al (US Publication No. 2022/0165705) and Bhagavat et al (US Publication No. 2019/0326273) and in further view of Chang et al (US Publication No. 2021/0265273).
Regarding claim 3, Wan discloses all the limitations but silent on the specific arrangement of the die. Whereas Chang discloses wherein the first supporter and the first die are combined to form a composite layer with at least one via passing through the first die and the first supporter Fig 4. Wan and Chang are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Wan and incorporate the teachings of Chang to improve device performance ¶0002-0005 .
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al (US Publication No. 2021/0118756) in view of Bean et al (US Publication No. 2022/0165705) and Bhagavat et al (US Publication No. 2019/0326273) and in further view of Tsai et al (US Publication No. 2022/0157732).
Regarding claim 5, Wan discloses all the limitations but silent on the specific arrangement of the package. Whereas Tsai discloses wherein the backside of the first die is located in close proximity to the first supporter and the front side of the first die is farther away from the first supporter compared to the backside, and the semiconductor package further comprises: a global interconnect disposed on the backside of the first die; and a first re-distribution layer (RDL) disposed on the global interconnect; and a second RDL on a first side of the first supporter facing the first die; wherein the first die and the first supporter are bonded through the first RDL and the second RDL Fig 3. Wan and Tsai are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Wan and incorporate the teachings of Tsai to improve device performance.
Regarding claim 14, Tsai discloses wherein the second supporter further comprises: a fifth RDL on a first side of the second supporter; and a sixth RDL on a second side of the second supporter opposite to the first side, wherein the through via electrically or optically connects the fifth RDL and the sixth RDL Fig 3.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al (US Publication No. 2021/0118756) in view of Bean et al (US Publication No. 2022/0165705), Bhagavat et al (US Publication No. 2019/0326273)and Tsai et al (US Publication No. 2022/0157732) and in further view of Yazdani (US Publication No. 2015/0287672).
Regarding claim 6, Wan discloses all the limitations but silent on the specific arrangement of the package. Whereas Yazdani discloses a third RDL on a second side of the first supporter opposite to the first side; a first thermal via in the first supporter, connecting the second RDL and the third RDL; and a first power via and a first signal via in the first supporter, connecting the second RDL and the third RDL Fig 11A-17. Wan and Yazdani are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Wan and incorporate the teachings of Yazdani to improve device performance.
Regarding claim 7, Yazdani discloses a buried power rail proximal to a front-end-of-line (FEOL) structure of the first die; a power trace and a signal trace in the global interconnect, electrically connected to the buried power rail and to the FEOL structure, respectively; and a second thermal via proximal to the power and signal trace in the global interconnect and the FEOL structure of the first die, wherein the second thermal via is thermally coupled to the first thermal via in the first supporter ¶0063-0066 Fig 11A-17.
Regarding claim 8, Yazdani discloses a fourth RDL containing conductive traces over the front side of the first die, wherein a heat spreading layer or a thermal isolation layer is formed in the fourth RDL, in a back-end-of-line (BEOL) structure proximal to the front side of the first die, in the global interconnect of the first die, or in a front-end-of-line (FEOL) structure proximal to the front side of the first die ¶0063-0066 Fig 11A-17.
Allowable Subject Matter
Claims 16-21 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “a plurality of memory dies and control dies stacked over the processor die/first HTC structure; and a second HTC structure between the processor die and control dies, or between adjacent memory dies, wherein a thermal conductivity of the second HTC structure is greater than the thermal conductivity of the processor die”, as recited in independent claims 16 and 21.
Claims 17-20 are also allowed as being directly or indirectly dependent of the allowed independent base claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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