DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species B in the reply filed on March 16, 2026 is acknowledged.
Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 16, 2026.
It is noted for clarity of the record that claim 10 requires the interposer to comprise a dummy pad. However, elected species B, as drawn to Fig 3B, only has contact pads shown in the interposer. Further, [0044] discloses dummy pads in the interposer in Fig 3A but no other figures with regards to the interposer.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, the claim recites the limitation “the at least one test pad” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will interpret claim 6 to be dependent on claim 5.
Claim 7 is also rejected as it is dependent on claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 12-14, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20130087925 A1), hereinafter Tsai, in view of Chun et. al. (US 20210202430 A1), hereinafter Chun.
Regarding claim 1, Tsai teaches a semiconductor package (not shown, [0019]; Examiner notes that Tsai teaches the semiconductor die is bonded to form a package, such as Fig 6), comprising: a semiconductor die (Fig 2 chip 20, [0009]) comprising a first region (Fig 2 region containing bumps 24A), a seal ring region (embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]) surrounding the first region (Fig 2 region containing bumps 24A), and a second region (Fig 2 region containing bumps 24B) between the seal ring region (embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]) and a die edge (Fig 2 edges 20A, [0009]) of the semiconductor die (Fig 2 chip 20, [0009]); an interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) disposed below (Examiner notes It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the location of the interposer can be below instead of above as shown in Tsai) the semiconductor die (Fig 2 chip 20, [0009]); first joints (Fig 2 bumps 24A, [0010]) electrically coupling (active, [0010]) the semiconductor die (Fig 2 chip 20, [0009]) to the interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]), the first joints (Fig 2 bumps 24A, [0010]) being located within the first region (Fig 2 region containing bumps 24A); at least one second joint (Fig 2 bumps 24B, [0010]) coupling the semiconductor die (Fig 2 chip 20, [0009]) to the interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]), the at least one second joint (Fig 2 bumps 24B, [0010]) being disposed at a die corner (Fig 2 corner 20B, [0009]) within the second region (Fig 2 region containing bumps 24B), and the at least one second joint (Fig 2 bumps 24B, [0010]) being electrically floating ([0019]) in the semiconductor package (not shown, [0019]).
Tsai fails to teach a first underfill disposed between the semiconductor die and the interposer to surround the first joints and the at least one second joint.
However, Chun teaches a first underfill (not shown, [0035]) disposed between ([0035]) the semiconductor die (Fig 1A semiconductor die 102, [0035] corresponds to Tsai: Fig 2 chip 20, [0009]) and the interposer (Fig 1A package substrate 104, [0035] corresponds to Tsai: Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) to surround ([0039]) the first joints (Fig 1A inner interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24A, [0010]) and the at least one second joint (Fig 1A outer interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24B, [0010]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai to incorporate the teachings of Chun by having an underfill material. This would reduce the vibrational stresses on the interconnect structure (Fig 4 structure with metal lines 42 and via 44, [0019]) (joints) during manufacturing ([0046]).
Regarding claim 2, Tsai as modified in claim 1 teaches the semiconductor die (Fig 2 chip 20, [0009]) further comprises: first (Fig 4 unlabeled pads under bumps 24B away from the corner in Fig 2; See note below) and second dummy pads (Fig 4 bumps 24B in the corner in Fig 2) arranged within the second region (Fig 2 region containing bumps 24B), the at least one second joint (Fig 2 bumps 24B, [0010]) landing on one of the second dummy pads (Fig 4 bumps 24B in the corner in Fig 2); and a passivation layer (Fig 4 layer above dielectric layer 56, [0017]; See note below) extending across the first region (Fig 2 region containing bumps 24A), the seal ring region (embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]), and the second region (Fig 2 region containing bumps 24B), and the passivation layer (Fig 4 layer above dielectric layer 56, [0017]; See note below) partially covering (sides are covered) the first (Fig 4 unlabeled pads under bumps 24B away from the corner in Fig 2) and second dummy pads (Fig 4 bumps 24B in the corner in Fig 2).
Examiner notes that Tsai teaches a dielectric layer 56 ([0017]-[0018]). However, Tsai is silent on the layer above dielectric layer 56. Examiner interprets the layer above dielectric layer 56 to be a passivation layer, as one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the top most layer with an unlabeled solder pad to be a passivation layer.
Regarding claim 3, Tsai as modified in claim 2 fails to teach the first underfill extends into openings of the passivation layer to be in direct contact with the first dummy pads.
Regarding the choice of having the first underfill extending into openings of the passivation layer to be in direct contact with the first dummy pads, this particular structure would have been obvious to try. As stated above, Tsai teaches there are dummy joints and dummy pads to absorb stresses in packaging ([0005]). Further, Tsai teaches that the number of dummy joints can be dependent on the stress applied ([0011]). In pursuing this arrangement in the device of Tsai, there are only two choices for the structure in direct contact with the dummy pads: with a dummy joint or with an underfill material. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the dummy pad would function the same, regardless of which of these two structures is chosen. Additionally, one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to save on solder material by not having minimal joints over the dummy pads. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 4, Tsai as modified in claim 2 teaches a semiconductor substrate (Fig 4 semiconductor substrate 40, [0016])and an interconnect structure (Fig 4 structure with metal lines 42 and via 44, [0019]) disposed between (Fig 4) the semiconductor substrate (Fig 4 semiconductor substrate 40, [0016]) and the passivation layer (Fig 4 passivation layer 56, [0018]), and the first (Fig 4 unlabeled pads under bumps 24B away from the corner in Fig 2) and second dummy pads (Fig 4 unlabeled pad for bumps 24B in the corner in Fig 2) are in direct contact (Fig 4) with an interconnect dielectric layer (Fig 4 dielectric layer 56, [0017]; Examiner considers dielectric layer to be part of the interconnect dielectric layer since Tsai teaches the dashed line 58 indicates electrical coupling; this would require additional conductive traces not shown and dielectric material surrounding the conductive traces) of the interconnect structure (Fig 4 structure with metal lines 42 and via 44, [0019]).
Regarding claim 9, Tsai as modified in claim 1 teaches the at least one second joint (Tsai: Fig 2 bumps 24B, [0010]) comprises a first end (Tsai: Fig 4 end connected to a pad) connected to a dummy pad (Tsai: Fig 4 unlabeled pad for bumps 24B in the corner in Fig 2) of the semiconductor die (Tsai: Fig 2 chip 20, [0009]) and a second end (Tsai: Fig 4 end opposite first end) opposite to the first end (Tsai: Fig 4 end connected to a pad).
Tsai as modified in claim 1 fails to teach a substantial entirety of the second end is directly connected to a dielectric layer of the interposer.
Regarding the choice of connecting a substantial entirety of the second end of the at least one second joint direct to a dielectric layer of the interposer. Chun teaches interconnect structures can be coupled to insulating material of a semiconductor die (claim 12). Further, Chun teaches the interconnect structure can be dummy structures not electrically coupling the semiconductor die and package substrate or electrically coupling the semiconductor die and package substrate ([0032]). In addition, Chun teaches the package substrate can include the similar electrical elements coupled to the package substrate that can then be further coupled with the interconnect structures ([0031]). In pursuing the coupling, there are only four arrangements in the modified device of Tsai to achieve this result: both substrates have a dummy pad, a dummy pad on the semiconductor die and a dielectric layer on the package substrate, a dielectric layer on the semiconductor die and a dummy pad on the package substrate, or a dielectric layer on both the semiconductor die and package substrate. One having ordinary skill in the art would recognize that the coupling would be achieved equally, regardless of which of these combinations is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 12, Tsai teaches a semiconductor package (not shown, [0019]; Examiner notes that Tsai teaches the semiconductor die is bonded to form a package), comprising: a first package component (Fig 2 chip 20, [0009]) comprising: active pads (Fig 2 pads for bumps 24A); and a dummy pad structure (Fig 2 region containing pads for bumps 24B) comprising first dummy pads (Fig 2 pads for bumps 24B; See annotated figure) disposed at a die corner (Fig 2 corner 20B) and second dummy pads (Fig 4 pads for bumps 24B; See annotated figure) disposed alongside the first dummy pads (Fig 2 pads for bumps 24B; See annotated figure) and between the active pads (Fig 2 pads for bumps 24A) and a die edge (Fig 2 edges 20A, [0009]); a second package component (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) disposed below (Examiner notes It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the location of the interposer can be below instead of above as shown in Tsai) the first package component (Fig 2 chip 20, [0009]) and electrically coupled (active, [0010]) to the first package component (Fig 2 chip 20, [0009]) through first joints (Fig 2 bumps 24A, [0010]) coupled to the active pads (Fig 2 pads for bumps 24A); second joints (Fig 2 bumps 24B, [0010]) coupled to the first dummy pads (Fig 2 pads for bumps 24B; See annotated figure) and anchoring (See below) the second package component (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]).
Tsai fails to teach an underfill disposed between the first and second package components and laterally covering the first joints and the second joints, the underfill being in contact with at least a portion of the second dummy pads.
However, Chun teaches an underfill (not shown, [0035]) disposed between ([0035]) the first (Fig 1A semiconductor die 102, [0035] corresponds to Tsai: Fig 2 chip 20, [0009]) and second package components (Fig 1A package substrate 104, [0035] corresponds to Tsai: Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) to laterally covering ([0039]) the first joints (Fig 1A inner interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24A, [0010]) and the second joints (Fig 1A outer interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24B, [0010]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai to incorporate the teachings of Chun by having an underfill material. This would reduce the vibrational stresses on the interconnect structure during manufacturing ([0046]).
In modifying Tsai with the teachings of Chun, the underfill (not shown, [0035]) would be in contact (electrical contact; not direct contact) with at least a portion of the second dummy pads (Fig 4 pads for bumps 24B; See annotated figure).
Regarding the anchoring by the second joints. Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
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Regarding claim 13, Tsai as modified in claim 12 teaches a seal ring structure (Tsai: embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]) separating the active pads (Tsai: Fig 2 pads for bumps 24A) from the first dummy pads (Tsai: Fig 2 pads for bumps 24B; See annotated figure of claim 12) and the second dummy pads (Tsai: Fig 2 pads for bumps 24B; See annotated figure of claim 12).
Regarding claim 14, Tsai as modified in claim 12 teaches a passivation layer (Tsai: Fig 4 layer above dielectric layer 56, [0017]; See note below) with openings (Tsai: Fig 4 openings have pads under bumps 24A/B), the passivation layer (Tsai: Fig 4 layer above dielectric layer 56, [0017]; See note below) partially covers (Tsai: covers the side) the first dummy pads (Tsai: Fig 2 pads for bumps 24B; See annotated figure), the second dummy pads (Tsai: Fig 4 bumps 24B in the corner in Fig 2), and the active pads (Tsai: Fig 2 pads for bumps 24A), and
Tsai fail to teach the underfill extends into a portion of the openings of passivation layer to be in direct contact with the second dummy pads.
Examiner notes that Tsai teaches a dielectric layer 56 ([0017]-[0018]). However, Tsai is silent on the layer above dielectric layer 56. Examiner interprets the layer above dielectric layer 56 to be a passivation layer, as one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the top most layer with an unlabeled solder pad to be a passivation layer.
Regarding the choice of having the underfill extends into a portion of the openings of passivation layer to be in direct contact with the second dummy pads, this particular structure would have been obvious to try. As stated above, Tsai teaches there are dummy joints and dummy pads to absorb stresses in packaging ([0005]). Further, Tsai teaches that the number of dummy joints can be dependent on the stress applied ([0011]). In pursuing this arrangement in the device of Tsai, there are only two choices for the structure in direct contact with the dummy pads: with a dummy joint or with an underfill material. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the dummy pad would function the same, regardless of which of these two structures is chosen. Additionally, one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to save on solder material by not having minimal joints over the dummy pads. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 21, Tsai teaches a semiconductor package (not shown, [0019]; Examiner notes that Tsai teaches the semiconductor die (Fig 2 chip 20, [0009]) is bonded to form a package), comprising: an interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]); a semiconductor die (Fig 2 chip 20, [0009]) disposed over the interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]), the semiconductor die (Fig 2 chip 20, [0009]) comprising a first region (Fig 2 region containing bumps 24A) and a second region (Fig 2 region containing bumps 24B) surrounding the first region (Fig 2 region containing bumps 24A); an active joint (Fig 2 bump 24A, [011]) electrically coupling (active, [0010]) the semiconductor die (Fig 2 chip 20, [0009]) to the interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]), the active joint (Fig 2 bump 24A, [011]) being located within the first region (Fig 2 region containing bumps 24A); a dummy joint (Fig 2 bump 24B, [011]) disposed within the second region (Fig 2 region containing bumps 24B) of the semiconductor die (Fig 2 chip 20, [0009]) and anchoring (See below) the interposer (Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]), and the dummy joint (Fig 2 bump 24B, [011]) being electrically floating ([0019]) in the semiconductor package (not shown, [0019]; Examiner notes that Tsai teaches the semiconductor die is bonded to form a package), wherein the active joint (Fig 2 bump 24A, [011]) and the dummy joint (Fig 2 bump 24B, [011]) comprise a solder material (solder, [0010]).
Tsai fails to teach an underfill surrounding the active joint and the dummy joint.
However, Chun teaches an underfill (not shown, [0035]) surrounding ([0039]) the active joint (Fig 1A inner interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24A, [0010]) and the dummy joint (Fig 1A outer interconnect structure 120, [0039] corresponds to Tsai: Fig 2 bumps 24B, [0010]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai to incorporate the teachings of Chun by having an underfill material. This would reduce the vibrational stresses on the interconnect structure (Fig 4 structure with metal lines 42 and via 44, [0019]) (joints) during manufacturing ([0046]).
Regarding the anchoring by the dummy joint. Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 22, Tsai as modified in claim 21 teaches the dummy joint (Tsai: Fig 2 bump 24B, [011]) comprises a first end (Fig 4 end connected to pad) connected to a dummy pad (Tsai: Fig 4 pad for bump 24B, [011]) of the semiconductor die (Tsai: Fig 4 chip 20, [0009]) and a second end (Fig 4 end opposite to end connected to pad) opposite to the first end (Fig 4 end connected to pad).
Tsai as modified in claim 21 fails to teach a second end connected to a dielectric layer of the interposer.
Regarding the choice of connecting a second end of the dummy joint a dielectric layer of the interposer. Chun teaches interconnect structures can be coupled to insulating material of a semiconductor die (claim 12). Further, Chun teaches the interconnect structure can be dummy structures not electrically coupling the semiconductor die and package substrate or electrically coupling the semiconductor die and package substrate ([0032]). In addition, Chun teaches the package substrate can include the similar electrical elements coupled to the package substrate that can then be further coupled with the interconnect structures ([0031]). In pursuing the coupling, there are only four arrangements in the modified device of Tsai to achieve this result: both substrates have a dummy pad, a dummy pad on the semiconductor die and a dielectric layer on the package substrate, a dielectric layer on the semiconductor die and a dummy pad on the package substrate, or a dielectric layer on both the semiconductor die and package substrate. One having ordinary skill in the art would recognize that the coupling would be achieved equally, regardless of which of these combinations is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 23, Tsai as modified in claim 22 teaches an area of the second end (Chun: Fig 1A end coupling to package substrate 104) of the dummy joint (Chun: Fig 1A interconnect structure 120, [0032] corresponds to Tsai: Fig 4 bump 24B, [0011]) connected to the dielectric layer (Chun: not labeled on interposer 104; package substrate can contain similar electrical elements as semiconductor die, [0031]) of the interposer (Tsai: Fig 6 not labeled; however, chip 20 is connected to an interposer, [0010]) is greater (Chun: Fig 1A; Examiner notes that Tsai teaches the bump 24 may be copper pillars, solder caps, and the like, [0010]; these structures are similar to Chun and when there is pressure applied the second end swells, as shown in Chun Fig 1A) than an area of the first end (Chun: Fig 1A end coupling to semiconductor die 102, [0032] corresponds to Tsai: Fig 4 end connected to pad for bump 24B) of the dummy joint (Chun: Fig 1A interconnect structure 120, [0032] corresponds to Tsai: Fig 4 bump 24B, [0011]) connected to the dummy pad (Chun: not shown, [0032] corresponds to Tsai: Fig 4 pad for bump 24B) of the semiconductor die (Tsai: Fig 2 chip 20, [0009]).
Regarding claim 24, Tsai as modified in claim 22 teaches the underfill (Chun: not shown, [0035]) is connected to (the underfill surrounds the joints so it would contact both surfaces on the top and bottom) the passivation layer (Tsai: Fig 4 layer above dielectric layer 56, [0017]; See note below) of the semiconductor die (Fig 2 chip 20, [0009]) and the dielectric layer (from modification of claim 22) of the interposer (Fig 6 not labeled; however, chip 20 is connected to an interposer, [0010]).
Tsai as modified in claim 22 fails to teach a passivation layer overlying the dummy pad, the dummy joint passes through the passivation layer to be in contact with the dummy pad.
However, Tsao teaches a passivation layer (Fig 1 passivation layer 1023, [0026] corresponds to Tsai: Fig 4 layer above dielectric layer 56, [0017]) overlying the dummy pad (Fig 1 bond pad 1022, [0026] corresponds to Tsai: Fig 4 pad for bump 24B, [011]), the dummy joint (Fig 1 structure with UBM structure 1021, [0027]; conductive bump 103, [0027]; and metal cap layer 105, [0029] corresponds to Tsai: Fig 4 bump 24B, [0011]) passes through the passivation layer (Fig 1 passivation layer 1023, [0026] corresponds to Tsai: Fig 4 layer above dielectric layer 56, [0017]) to be in contact with the dummy pad (Fig 1 bond pad 1022, [0026] corresponds to Tsai: Fig 4 pad for bump 24B, [011]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the structure of Tsai in Fig 4 meets these limitations, as there is an additional unlabeled material layer on top of the pads underneath the bumps 24A/B. This material likely performs the same function as the passivation overlying the pads.
Regarding claim 25, Tsai as modified in claim 21 teaches a passivation layer (Tsai: Fig 4 layer above dielectric layer 56, [0017]; See note below) and a seal ring structure (Tsai: embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]) separating the first region (Tsai: Fig 2 region containing bumps 24A) from the second region (Tsai: Fig 2 region containing bumps 24B), and the passivation layer (Tsai: Fig 4 layer above dielectric layer 56, [0017]; See note below) and the seal ring structure (Tsai: embodiment with Fig 2 not shown region with seal ring 30 that encircles bumps 24A, [0011]) are in contact (electrical contact; not direct contact) with the underfill (Chun: not shown, [0035]).
Examiner notes that Tsai teaches a dielectric layer 56 ([0017]-[0018]). However, Tsai is silent on the layer above dielectric layer 56. Examiner interprets the layer above dielectric layer 56 to be a passivation layer, as one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the top most layer with an unlabeled solder pad to be a passivation layer.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20130087925 A1), hereinafter Tsai, in view of Chun et. al. (US 20210202430 A1), hereinafter Chun, in further view of Cheng et. al. (US 20140167199 A1), hereinafter Cheng.
Regarding claim 5, Tsai as modified in claim 1 fails to teach at least one test pad disposed within the second region and comprising a probe mark, and the first underfill directly covering the probe mark.
However, Cheng teaches a semiconductor die (Fig 1 semiconductor die 110, [0015] corresponds to Tsai: Fig 2 chip 20, [0009]) with at least one test pad (Fig 3 test pads 317, [0016]) disposed withing a second region (Fig 3 sealing ring structure 315, [0016] corresponds to Tsai: Fig 2 region containing bumps 24B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai and Chun to incorporate the teachings of Cheng by having test pads disposed within a second region. This would allow for testing of the semiconductor dies.
Once Tsai and Chun have been modified by Cheng there would be at least one test pad (Cheng: Fig 3 test pads 317, [0016]) disposed within the second region (Tsai: Fig 2 region containing bumps 24B) and comprising a probe mark (It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that a probe mark would occur when testing using a probe on a test pad), and the first underfill directly (Chun: Examiner notes the underfill surrounds the interconnect structures and It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the underfill would also cover the test pad since the test pad would be adjacent to an interconnect structure) covering the probe mark.
Regarding claim 6, Tsai as modified in claim 6 teaches the at least one test pad (Cheng: Fig 3 test pads 317, [0016]) comprises an array of test pads (Cheng: Fig 3 test pads 317 shown in an array, [0016]) arranged within the second region (Tsai: Fig 2 region containing bumps 24B), the second region (Tsai: Fig 2 region containing bumps 24B) comprises a dummy area (Tsai: corners of die 20; See annotated figure) other than a distributed area of the array of test pads (Cheng: Fig 3 test pads 317 shown in an array, [0016]), and the dummy area (Tsai: corners of die 20) comprises a forbidden zone (Tsai: area in the corner of die 20; See annotated figure) in which the at least one second joint (Tsai: Fig 2 bumps 24B, [0010]) is located.
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Regarding claim 7, Tsai as modified in claim 6 teaches an array of dummy pads (Tsai: Fig 4 unlabeled pads under bumps 24B away from the corner in Fig 2) arranged in the dummy area (See annotated figure of claim 6) other than the forbidden zone (See annotated figure of claim 6), wherein a distribution area of the array of dummy pads (area for two dummy pads) in the dummy area is greater (area for 2 pads > area for 1 pad) than an area (area for one dummy pad) of the at least one second joint (Tsai: Fig 2 bumps 24B, [0010]) in the dummy area (Tsai: Fig 4 unlabeled pad for bumps 24B in the corner in Fig 2).
Examiner notes that Tsai teaches there may be more than three dummy bumps ([0011]). This would result in the corners having more than three dummy pads.
Regarding claim 8, Tsai as modified in claim 5 teaches the first underfill (Chun: Examiner notes the underfill surrounds the interconnect structures and It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the underfill would also cover the test pad since the test pad would be adjacent to an interconnect structure) is in contact with the at least one test pad (Cheng: Fig 3 test pads 317, [0016]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20130087925 A1), hereinafter Tsai, in view of Chun et. al. (US 20210202430 A1), hereinafter Chun, in further view of Huang et. al. (US 20200203300 A1), hereinafter Huang.
Tsai as modified in claim 1 fails to teach a circuit substrate disposed below and electrically coupled to the interposer through solder joints; and a second underfill disposed between the interposer and the circuit substrate and surrounding the solder joints.
However, Huang teaches a circuit substrate (Fig 1G substrate 190, [0077]) disposed below and electrically coupled ([0076]) to the interposer (Fig 1G substrate 110, [0022] corresponds to Tsai: Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) through solder joints (Fig 1G solder balls 182b, [0070]); and a second underfill (Fig 1G underfill layer 210, [0082]) disposed between the interposer (Fig 1G substrate 110, [0022] corresponds to Tsai: Fig 6 not labeled; however chip 20 is connected to an interposer, [0010]) through solder joints (Fig 1G solder balls 182b, [0070]) and the circuit substrate (Fig 1G substrate 190, [0077]) and surrounding the solder joints (Fig 1G solder balls 182b, [0070]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai and Chun to incorporate the teachings of Huang by having a circuit substrate, solder joints, and a second underfill to couple with the interposer. This would enable the formation of a 3DIC package, as was known in the art before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20130087925 A1), hereinafter Tsai, in view of Chun et. al. (US 20210202430 A1), hereinafter Chun, in view of Tsao et. al. (US 20160148891 A1), hereinafter Tsao.
Tsai as modified in claim 12 teaches the first dummy pads (Tsai: Fig 2 pads for bumps 24B; See annotated figure of claim 12), the second dummy pads (Tsai: Fig 2 pads for bumps 24B; See annotated figure of claim 12), and the active pads (Tsai: Fig 2 pads for bumps 24A) are disposed at a same level (Tsai: Fig 4) in the first package component (Tsai: Fig 2 chip 20, [0009]).
Tsai as modified in claim 12 fails to teach the pads comprise a same material.
However, Tsao teaches bond pads (Fig 1 bond pad 1022, [0026]) disposed at a same level in the first package component (Fig 1 semiconductor chip 102, [0026]) and comprising a same material ([0026]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai and Chun to incorporate the teachings of Tsao by have the pads comprise a same material. This would reduce manufacturing time since the pads would be made at the same time from the same material.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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