Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I in the reply filed on March 11, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho (Pub. No. US 20130207267 A1), in view of McTeer (US Patent No. 6,278,188).
Regarding claim 1, Rho teaches a method for manufacturing a semiconductor device, comprising: forming a plurality of sacrificial stack portions on a semiconductor substrate, the plurality of sacrificial stack portions being spaced apart from each other (Fig. 2, semiconductor substrate 100, mold layer 400, trenches 411; ¶34-37); forming a metal material layer to cover the plurality of sacrificial stack portions, the metal material layer including a first metal and a second metal different from the first metal (Fig. 3, first metal layer 510; ¶38-39); and annealing the metal material layer to form a self-forming barrier layer conformally covering the plurality of sacrificial stack portions, the self-forming barrier layer including a metal oxide, metal silicide, or a combination thereof formed from the first metal by annealing (Fig. 4, first metal layer 510, sidewall protection layer 511; ¶40-42). However, Rho does not explicitly teach the first metal having a reduction potential lower than a reduction potential of the second metal.
McTeer teaches the first metal having a reduction potential lower than a reduction potential of the second metal (Col. 3, lines 15-38).
Rho and McTeer are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of McTeer to have the first metal have a reduction potential lower than a reduction potential of the second metal. For the purpose of protecting the metal with the higher reduction potential from damage during manufacturing processes such as chemical-mechanical polishing, as recognized by McTeer.
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Claim(s) 2-4, 6-7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer as applied to claim 1 above, and further in view of Huang et al. (Pub. No. CN 114883250 A), hereinafter referred to as Huang, and in further view of Engel et al. (Pub. No. US 20120306093 A1), hereinafter referred to as Engel.
Regarding claim 2, Rho further teaches the method further comprising a planarization process to form a plurality of metal line structures spaced apart from each other by the sacrificial portions (Fig. 6, mold layer 400, second metal lines 535; ¶44); and one of the plurality of metal line structures including a bulk metal portion, and a self-forming barrier formed from the self-forming barrier layer to laterally cover the bulk metal portion and the bottom surface of the bulk metal portion (Fig. 6, second metal lines 535, sidewall protection layer 511; ¶44). However, Rho does not teach the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions. Rho also does not teach a self-forming etch stop portion disposed on the bulk metal portion. The self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
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Huang teaches the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate (Fig. 1F, conductive layer 112, hard mask 114; ¶72).
Rho, McTeer, and Huang are all analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of McTeer to incorporate the teachings of Huang to have the plurality of sacrificial stack potions include a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate. Also removing the plurality of hard mask portions of the plurality of sacrificial stack potions during the planarization process to expose the plurality of sacrificial metal portion of the plurality of sacrificial stack portions. Changing the composition of the stack for the purpose of preventing unwanted reactions during the annealing process and being able to remove the sacrificial metal layer using an oxidant such as hydrogen peroxide.
However, Rho, McTeer, and Huang don’t teach a self-forming etch stop portion disposed on the bulk metal portion. The self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
Engel teaches a self-forming etch stop portion including a metal oxide formed by oxidation of the metal in the planarization process (Fig. 4, etch stop layer 150; ¶17).
Rho, McTeer, Huang, and Engel are all analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of McTeer and in further view of Huang to incorporate the teachings of Engel to create a self-forming etch stop portion disposed on the bulk metal portion, and the self-forming etch stop portion includes a metal oxide formed by oxidation of the first metal in the planarization process. For the purpose of simplifying the manufacturing process by forming an etch stop layer during the planarization process and avoiding additional deposition steps.
Regarding claim 3, Rho further teaches before formation of the plurality of sacrificial stack portions, forming a via layer on the semiconductor substrate, the via layer including a via structure exposing from a first trench formed between two corresponding ones of the plurality of sacrificial stack portions (Figs. 1 & 2, semiconductor substrate 100, first insulating layer 210, etch stop 240, contact plugs 300, trench 411; ¶30-37); and after forming the plurality of sacrificial stack portions, forming a sidewall spacer on the via structure and on the plurality of sacrificial stack portions and removing the sidewall spacer to expose the via structure to be connected to a corresponding one of the plurality of metal line structures (Fig. 10, sidewall spacers 1520; ¶54). However, Rho does not teach explicitly teach the formation of a cap layer on the via structure or forming an oxidation prevention layer on the plurality of sacrificial stack portions. Huang teaches selectively forming a cap layer on the via structure (Fig. 1D, cover layer 108; ¶70); and conformally forming an oxidation prevention layer on the plurality of sacrificial stack portions (Fig. 1G, capping layer 118; ¶74).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to add a cover layer and capping layer into the method of Rho so that the method further comprises that after the formation of the plurality of sacrificial stack portions, selectively forming a cap layer on the via structure, conformally forming an oxidation prevention layer on the plurality of sacrificial stack portions such that the cap layer is exposed, and removing the cap layer to expose the via structure to be connected to a corresponding one the of the plurality of metal line structures. For the purpose of protecting the semiconductor device from damage and undesired oxidation during manufacturing.
Regarding claim 4, Rho further teaches removing the sacrificial portions to form a plurality of second trenches among the plurality of metal line structures, one of the plurality of second trenches having a width decreasing gradually in a direction from a lower surface to an upper surface of one of the plurality of metal line structures (Fig. 8, empty gaps 403, second metal lines 535; ¶46-48, 50); and forming a dielectric layer to cover the plurality of metal line structures, the dielectric layer including a lower dielectric layer portion and an upper dielectric layer portion deposed on and in direct contact with the lower dielectric layer portion (Fig. 9, second insulation layer 450, second metal lines 535; ¶49-52). However, Rho doesn’t teach the sacrificial portions having sacrificial metal portions.
Huang teaches the sacrificial portions having sacrificial metal portions (Fig. 1F, conductive layer 112; ¶).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to have the sacrificial portion include sacrificial metal portions. For the purpose of preventing unwanted reactions during the annealing process and being able to remove the sacrificial metal layer using an oxidant such as hydrogen peroxide.
Regarding claim 6, Rho further teaches the first metal being subjected to oxidation, siliconization, or a combination thereof in annealing the metal material layer, such that the self-forming barrier layer in conformally formed. However, Rho does not teach an oxidation prevention layer.
Huang teaches having an oxidation prevention layer (Fig. 1G, capping layer 118; ¶74).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to include an oxidation prevention layer such that the self- forming barrier layer is conformally formed on the oxidation prevention layer. For the purpose of protecting the semiconductor device from damage and undesired oxidation during manufacturing.
Regarding claim 7, Rho further teaches a planarization process which is performed by a chemical mechanical polishing process (Fig. 6; ¶44). However, Rho does not teach the chemical mechanical polishing process using a slurry including an oxidant, such that the oxidation of the first metal in the planarization process is performed by the oxidant.
Engel teaches a chemical mechanical polishing process using a slurry including an oxidant, such that the oxidation of the first metal in the planarization process is performed by the oxidant (Fig. 4; ¶17).
Rho and Engel are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Engel to have the chemical mechanical polishing process use a slurry including an oxidant, such that the oxidation of the first metal in the planarization process is performed by the oxidant. For the purpose of simplifying the manufacturing process by forming an etch stop layer during the planarization process and avoiding additional deposition steps.
Regarding claim 9, Rho further teaches the plurality of metal line structures being formed in the lower dielectric layer portion of the dielectric layer (Fig. 9, second insulating layer 450, second metal lines 535; ¶49-52). However, Rho does not teach forming a plurality of interconnect structures in the upper dielectric layer portion of the dielectric layer, such that at least one of the plurality of interconnect structures is respectively connected to at least one of the plurality of metal line structures.
Huang teaches forming a plurality of interconnect structures in the upper dielectric layer portion of the dielectric layer, such that at least one of the plurality of interconnect structures is respectively connected to at least one of the plurality of metal line structures (Fig. 1T, dielectric material 134, conductive component 144, conductive layer 112; ¶91-93).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to form a plurality of interconnect structures in the upper dielectric layer portion of the dielectric layer, such that at least one of the plurality of interconnect structures is respectively connected to at least one of the plurality of metal line structures. For the purpose of creating a back-end-of-line interconnect structure with reduced RC time constant, as recognized by Huang.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, Huang, and Engel as applied to claim 4 above, and further in view of Cheng et al. (US Patent No. 10,490,447), hereinafter referred to as Cheng.
Regarding claim 5, Rho teaches an upper end of one of the plurality of second trenches having a width less than the lower end (Fig. 2, trenches 411; ¶50); and the dielectric layer is formed by physical vapor deposition or chemical vapor deposition using a low-k dielectric material including silicon oxide, silicon oxycarbide, or a combination thereof, such that a plurality of air gaps are formed among the plurality of metal line structures (Fig. 9, second insulation layer 450, air gaps 405; ¶49-52). However, Rho does not teach the upper end of one of the plurality of second trenches having a width less than 35 nm.
Cheng teaches the upper end of one of the plurality of second trenches having a width less than 35 nm (Figs. 11 & 12, trench openings 33, sidewall spacers 18; Col. 1, lines 34-42, Col. 8, lines 5-18, and Col. 10, lines 35-65).
Rho and Cheng are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Cheng to have the upper end of one of the plurality of second trenches having a width less than 35 nm. For the purpose of forming air gaps when depositing the dielectric material, as recognized by Cheng.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer as applied to claim 1 above, and further in view of Pabelico et al. (Pub. No. WO 2015172089 A1), hereinafter referred to as Pabelico.
Regarding Claim 8, Rho teaches the metal material layer including a cobalt alloy (Fig. 3, first metal layer 510; ¶38-39). However, Rho does not teach the metal material layer including an alloy represented by AxBy, wherein x is an integer ranging from 1 to 5, y is an integer ranging from 1 to 10, A represents the first metal including one of aluminum, chromium, manganese, zirconium, niobium, and combinations thereof, and B represents the second metal including one of ruthenium, copper, cobalt, and combinations thereof.
Pabelico teaches the metal material layer selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys thereof (Pg. 3, lines 3-5).
Rho and Pabelico are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Pabelico such that the metal material layer includes an alloy represented by AxBy, wherein x is an integer ranging from 1 to 5, y is an integer ranging from 1 to 10, A represents the first metal including one of aluminum, chromium, manganese, zirconium, niobium, and combinations thereof, and B represents the second metal including one of ruthenium, copper, cobalt, and combinations thereof. For the purpose of creating a back-end-of-line interconnect structure with reduced RC time constant.
Claim(s) 21, 22, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Chen et al. (Pub. No. US 20210020507 A1), hereinafter referred to as Chen.
Regarding claim 21, Rho teaches A method for manufacturing a semiconductor device, comprising: forming a plurality of sacrificial stack portions on a semiconductor substrate, the plurality of sacrificial stack portions being spaced apart from each other (Fig. 2, semiconductor substrate 100, mold layer 400, trenches 411; ¶34-37); forming a first metal material layer to cover the plurality of sacrificial stack portions, the first metal material layer including a first metal and a second metal different from the first metal (Fig. 3, first metal layer 510; ¶38-39); annealing the first metal material layer to form a self-forming barrier layer conformally covering the plurality of sacrificial stack portions, the self-forming barrier layer including a metal oxide, a metal silicide, or a combination thereof formed from the first metal by annealing (Fig. 4, first metal layer 510, sidewall protection layer 511; ¶40-42); and forming a second metal material layer (Fig. 5, second metal layer 530, ¶43).
However, Rho does not teach the first metal having a reduction potential lower than a reduction potential of the second metal. Rho also does not teach forming a second metal material layer on the first metal material layer opposite to the self- forming barrier layer.
McTeer teaches the first metal having a reduction potential lower than a reduction potential of the second metal (Col. 3, lines 15-38).
Rho and McTeer are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of McTeer to have the first metal have a reduction potential lower than a reduction potential of the second metal. For the purpose of protecting the metal with the higher reduction potential from damage during manufacturing processes such as chemical-mechanical polishing, as recognized by McTeer.
However, Rho in view of McTeer does not teach forming a second metal material layer on the first metal material layer opposite to the self-forming barrier layer. Chen teaches forming a second metal material layer on the first metal material layer opposite to the self-forming barrier layer (Fig. 4, metal 404, metal liner 124, barrier layer 302; ¶49-53).
Rho, McTeer, and Chen are all analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of McTeer to incorporate the teachings of Chen to form second metal material layer on the first metal material layer opposite to the self-forming barrier layer. For the purpose of having a metal material layer between the second metal material layer and the self-forming barrier layer which has benefits such as improving adhesion of the second metal material layer during its deposition.
Regarding claim 22, Rho further teaches performing a first planarization process to remove a portion of the second metal material layer and a portion of the sidewall protection layer, such that a remainder of the second metal material layer is recessed into and surround by a reminder of the sidewall protection layer (Fig. 6, second metal line 535, sidewall protection layer 511; ¶44).
However, Rho does not teach the planarization process removing a portion of the first metal material layer, such that a remainder of the second metal material layer is recessed into and surrounded by a remainder of the first metal material layer.
Chen teaches forming a second metal material layer on the first metal material layer opposite to the self-forming barrier layer (Fig. 4, metal 404, metal liner 124, barrier layer 302; ¶49-53).
Rho and Chen are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Chen to include a first metal material layer such that the planarization process removes a portion of the first metal material layer, such that a remainder of the second metal material layer is recessed into and surrounded by a remainder of the first metal material layer. For the purpose of having a metal material layer between the second metal material layer and the self-forming barrier layer which has benefits such as improving adhesion of the second metal material layer during its deposition.
Regarding claim 26, Rho further teaches the second metal material layer is different from the first metal material layer, and includes copper, cobalt, ruthenium, molybdenum, tungsten, or combinations thereof (Fig. 5, second metal layer 530; ¶43).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Chen as applied to claim 22 above, and further in view of Huang.
Regarding claim 23, Rho teaches removing a portion of the self-forming barrier layer by the first planarization process so as to expose a top portion of the sacrificial stack portion (Fig. 6, sidewall protection layer 511, mold layer 400; ¶44). However, Rho does not teach before formation of the first metal material layer, depositing an oxidation prevention layer on the plurality of sacrificial stack portions, such that the oxidation prevention layer is covered by the self-forming barrier layer after annealing the first metal material layer; and removing a portion of the self-forming barrier layer by the first planarization process so as to expose a top portion of the oxidation prevention layer.
Huang teaches depositing an oxidation prevention layer on the plurality of sacrificial stack portions (Fig. 1F, capping layer 118; ¶28).
Rho and Huang are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to include an oxidation prevention layer such that before formation of the first metal material layer, depositing an oxidation prevention layer on the plurality of sacrificial stack portions, such that the oxidation prevention layer is covered by the self-forming barrier layer after annealing the first metal material layer; and removing a portion of the self-forming barrier layer by the first planarization process so as to expose a top portion of the oxidation prevention layer. For the purpose of including an oxidation prevention layer to protect the semiconductor device from damage and undesired oxidation during manufacturing.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Chen as applied to claim 22 above, and further in view of Huang, and Engel.
Regarding claim 24, Rho teaches performing a planarization process to expose the plurality of sacrificial portions and to form a plurality of metal line structures spaced apart from each other by the plurality of sacrificial portions (Fig. 6, mold layer 400, second metal lines 535; ¶44); and one of the plurality of metal line structures includes a bulk metal portion, and a self-forming barrier formed from the self-forming barrier layer to laterally cover the bulk metal portion (Fig. 6, second metal lines 535, sidewall protection layer 511; ¶44). However, Rho does not teach the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate. Rho also does not teach a self-forming etch stop portion disposed on the bulk metal portion and a transition portion disposed between the bulk metal portion and the self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
Huang teaches the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate (Fig. 1F, conductive layer 112, hard mask 114; ¶72).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of McTeer to incorporate the teachings of Huang to have the plurality of sacrificial stack potions include a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate. Also removing the plurality of hard mask portions of the plurality of sacrificial stack potions during the planarization process to expose the plurality of sacrificial metal portion of the plurality of sacrificial stack portions. Changing the composition of the stack for the purpose of preventing unwanted reactions during the annealing process and being able to remove the sacrificial metal layer using an oxidant such as hydrogen peroxide.
However, Rho and Huang do not teach a self-forming etch stop portion disposed on the bulk metal portion and a transition portion disposed between the bulk metal portion and the self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
Engel teaches a self-forming etch stop portion disposed on the bulk metal portion and a transition portion disposed between the bulk metal portion and the self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process (Fig. 4, etch stop layer 150; ¶17).
Rho, Huang, and Engel are all analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of Huang and in further view of Engel to incorporate the teachings of Engel to create a self-forming etch stop portion disposed on the bulk metal portion and a transition portion disposed between the bulk metal portion and the self-forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process. Such that the self-forming barrier formed from the self-forming barrier layer to laterally covers the bulk metal portion, the transition portion, and the self-forming etch stop portion and to cover a bottom surface of the bulk metal portion. For the purpose of simplifying the manufacturing process by forming an etch stop layer during the planarization process and avoiding additional deposition steps.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Chen as applied to claim 21 above, and further in view of Pabelico.
Regarding claim 25, Rho teaches the first metal material layer including a cobalt alloy (Fig. 3, first metal layer 510; ¶38-39). However, Rho does not teach the first metal material layer including an alloy represented by AxBy, wherein x is an integer ranging from 1 to 5, y is an integer ranging from 1 to 10, A represents the first metal including one of aluminum, chromium, manganese, zirconium, niobium, and combinations thereof, and B represents the second metal including one of ruthenium, copper, cobalt, and combinations thereof.
Pabelico teaches the first metal material layer selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys thereof (Pg. 3, lines 3-5).
Rho and Pabelico are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Pabelico such that the first metal material layer includes an alloy represented by AxBy, wherein x is an integer ranging from 1 to 5, y is an integer ranging from 1 to 10, A represents the first metal including one of aluminum, chromium, manganese, zirconium, niobium, and combinations thereof, and B represents the second metal including one of ruthenium, copper, cobalt, and combinations thereof. For the purpose of creating a back-end-of-line interconnect structure with reduced RC time constant.
Claim(s) 27, 28, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Huang.
Regarding claim 27, Rho teaches a method for manufacturing a semiconductor device, comprising: forming a sacrificial stack on a semiconductor substrate (Fig. 1, semiconductor substrate 100, mold layer 400; ¶30-34); patterning the sacrificial stack to form a plurality of sacrificial stack portions on the semiconductor substrate, the plurality of sacrificial stack portions being spaced apart from each other (Fig. 2, mold layer 400, trenches 411; ¶35-37); forming a first metal material layer to cover the plurality of sacrificial stack portions, the first metal material layer including a first metal and a second metal different from the first metal (Fig. 3, first metal layer 510; ¶38-39); and annealing the first metal material layer to form a self-forming barrier layer conformally covering the plurality of sacrificial stack portions, the self-forming barrier layer including a metal oxide, a metal silicide, or a combination thereof formed from the first metal by annealing (Fig. 4, first metal layer 510, sidewall protection layer 511; ¶40-42).
However, Rho does not teach the sacrificial stack including a sacrificial metal layer and a hard mask layer disposed on the sacrificial metal layer opposite to the semiconductor substrate. Rho also does not teach the first metal having a reduction potential lower than a reduction potential of the second metal.
Huang teaches the sacrificial stack including a sacrificial metal layer and a hard mask layer disposed on the sacrificial metal layer opposite to the semiconductor substrate (Fig. 1E, conductive layer 112, hard mask 114; ¶71).
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to have the sacrificial stack include a sacrificial metal layer and a hard mask layer disposed on the sacrificial metal layer opposite to the semiconductor substrate. For the purpose of preventing unwanted reactions during the annealing process and being able to remove the sacrificial metal layer using an oxidant such as hydrogen peroxide.
However, Rho in view of Huang does not teach the first metal having a reduction potential lower than a reduction potential of the second metal.
McTeer teaches the first metal having a reduction potential lower than a reduction potential of the second metal (Col. 3, lines 15-38).
Rho and McTeer are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of McTeer to have the first metal have a reduction potential lower than a reduction potential of the second metal. For the purpose of protecting the metal with the higher reduction potential from damage during manufacturing processes such as chemical-mechanical polishing, as recognized by McTeer.
Regarding claim 28, Rho does not teach the sacrificial stack further including a glue layer disposed on the sacrificial metal layer opposite to the hard mask layer ().
Huang teaches the sacrificial stack further including a glue layer disposed on the sacrificial metal layer opposite to the hard mask layer (Fig. 1E, adhesive layer 110; ¶71).
Rho and Huang are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to include a glue layer disposed on the sacrificial metal layer opposite to the hard mask layer. For the purpose of improving the adhesion of the sacrificial metal layer during its deposition.
Regarding claim 30, Rho teaches forming sidewall spacers that cover the sacrificial layer and expose the contact plug (Fig. 10, sidewall spacers 1520, mold layer 1400, contact plugs 1300; ¶54). However, Rho does not teach before formation of the first metal material layer: forming a cap layer on the semiconductor substrate in a manner such that the plurality of sacrificial stack portions are exposed from the cap layer; and forming an oxidation prevention layer on the plurality of sacrificial stack portions in a manner such that the cap layer is exposed from the oxidation prevention layer.
Huang teaches before formation of the first metal material layer: forming a cap layer on the semiconductor substrate in a manner such that the plurality of sacrificial stack portions are exposed from the cap layer (Fig. 1D, cover layer 108; ¶70); and forming an oxidation prevention layer on the plurality of sacrificial stack portions. (Fig. 1G, capping layer 118; ¶74).
Rho and Huang are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Huang to form a cap layer on the semiconductor substrate in a manner such that the plurality of sacrificial stack portions are exposed from the cap layer and form an oxidation prevention layer on the plurality of sacrificial stack portions in a manner such that the cap layer is exposed from the oxidation prevention layer. For the purpose of protecting the semiconductor device using a cap layer and oxidation prevention layer.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Huang as applied to claim 27 above, and further in view of Chen.
Regarding claim 29, Rho teaches after formation of the self-forming barrier layer, forming a second metal material layer on the self-forming barrier layer opposite to the plurality of sacrificial stack portions (Fig. 5, second metal layer 530; ¶43). However, Rho does not teach forming the second metal material layer on the first metal material layer.
Chen teaches forming a second metal material layer on the first metal material layer opposite to the self-forming barrier layer (Fig. 4, metal 404, metal liner 124, barrier layer 302; ¶49-53).
Rho and Chen are analogous art as they are in the same field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho to incorporate the teachings of Chen to form second metal material layer on the first metal material layer opposite to the plurality of sacrificial stack portions. For the purpose of having a metal material layer between the second metal material layer and the self-forming barrier layer which has benefits such as improving adhesion of the second metal material layer during its deposition.
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rho in view of McTeer, and Huang as applied to claim 27 above, and further in view of Engel.
Regarding claim 31, Rho teaches performing a planarization process to form a plurality of metal line structures spaced apart from each other by the plurality of sacrificial portions and so as to expose the plurality of sacrificial portions (Fig. 6, mold layer 400, second metal lines 535; ¶44); and one of the plurality of metal line structures includes a bulk metal portion, and a self-forming barrier formed from the self-forming barrier layer to laterally cover the bulk metal portion (Fig. 6, second metal lines 535, sidewall protection layer 511; ¶44). However, Rho does not teach the plurality of sacrificial stack portions include a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate, the plurality of sacrificial metal portions being formed from the sacrificial metal layer, the plurality of hard mask portions being formed from the hard mask layer; the method further comprises performing a planarization process to remove the plurality of hard mask portions so as to expose the plurality of sacrificial metal portions and to form a plurality of metal line structures spaced apart from each other by the plurality of sacrificial metal portions; and one of the plurality of metal line structures includes a bulk metal portion, a self-forming etch stop portion disposed on the bulk metal portion, a transition portion disposed between the bulk metal portion and the self-forming etch stop portion, and a self-forming barrier formed from the self-forming barrier layer to laterally cover the bulk metal portion, the transition portion, and the self-forming etch stop portion and to cover a bottom surface of the bulk metal portion, the self- forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
Huang teaches the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate, the plurality of sacrificial metal portions being formed from the sacrificial metal layer, the plurality of hard mask portions being formed from the hard mask layer (Figs. 1E & 1F, conductive layer 112, hard mask 114; ¶71-72).
Rho and Huang are analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of McTeer to incorporate the teachings of Huang to have the plurality of sacrificial stack portions including a plurality of sacrificial metal portions and a plurality of hard mask portions respectively disposed on the plurality of sacrificial metal portions opposite to the semiconductor substrate, the plurality of sacrificial metal portions being formed from the sacrificial metal layer, the plurality of hard mask portions being formed from the hard mask layer. Such that the planarization process removes the plurality of hard mask portions so as to expose the plurality of sacrificial metal portions and to form a plurality of metal line structures spaced apart from each other by the plurality of sacrificial metal portions. Changing the composition of the stack for the purpose of preventing unwanted reactions during the annealing process and being able to remove the sacrificial metal layer using an oxidant such as hydrogen peroxide.
However Rho and Huang do not teach a self-forming etch stop portion disposed on the bulk metal portion, a transition portion disposed between the bulk metal portion and the self-forming etch stop portion, and a self-forming barrier formed from the self-forming barrier layer to laterally cover the bulk metal portion, the transition portion, and the self-forming etch stop portion and to cover a bottom surface of the bulk metal portion, the self- forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process.
Engel teaches a self-forming etch stop portion disposed on the bulk metal portion, a transition portion disposed between the bulk metal portion and the self-forming etch stop portion, the self- forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process (Fig. 4, etch stop layer 150; ¶17).
Rho, Huang, and Engel are all analogous art as they are in the field of endeavor of semiconductor manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Rho in view of Huang and in further view of Engel to incorporate the teachings of Engel to create a self-forming etch stop portion disposed on the bulk metal portion, a transition portion disposed between the bulk metal portion and the self-forming etch stop portion, the self- forming etch stop portion including a metal oxide formed by oxidation of the first metal in the planarization process. Such that the self-forming etch stop and transition portion are laterally covered by the self-forming barrier layer.
For the purpose of simplifying the manufacturing process by forming an etch stop layer during the planarization process and avoiding additional deposition steps.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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