Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (Pub. No. US 20210074783 A1) in view of Kim et al. (Pub. No. US 20200303479 A1), hereinafter referred to as Kang and Kim respectively.
Regarding claim 1, Kang teaches a display device comprising: a substrate (Fig. 12, substrate 110; ¶152-156, 215); a first semiconductor layer above the substrate, and comprising a first transistor and a second transistor (Fig. 12, transistors T1, T2, T5, T6, T7; ¶118-119, 126, 215, 221); a first gate conductive layer and a second gate conductive layer above the first semiconductor layer (Fig. 12, driving gate electrode G1, second electrode CE2; ¶121-127, 164, 172, 215, 222); a second semiconductor layer above the second gate conductive layer, and comprising a third transistor (Fig. 12, transistors T3, T4; ¶128-129, 215, 218, 220); a third gate conductive layer above the second semiconductor layer (Fig. 12, G4; ¶131-133, 215); a connection metal conductive layer above the insulating film, and comprising a first connection electrode electrically connecting the first transistor to the third transistor, the first connection electrode comprising a (1-1)-th region overlapping the first transistor, and a (1-2)-th region and a (1-3)-th region overlapping the third transistor, the (1-2)-th region and the (1-3)-th region being connected to the third transistor (Figs. 11a and 12, first interlayer insulating layer 114, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223); and a first data conductive layer and a second data conductive layer above the connection metal conductive layer (Fig. 12, data line DL, fire wire FL1′; ¶214-217, 225-229).
However, Kang does not explicitly teach an insulating film defining a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer.
Kim teaches an insulating film defining a valley surrounding the semiconductor layers and the first gate conductive layers (Figs. 4 and 5a, groove GR, organic filler 161; ¶85-87, 90-99, 141-145).
Kang and Kim are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the display device of Kang with the groove and organic filler of Kim such that the display device includes an insulating film defining a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer. For the purpose of better protecting the device from damage such as external shocks and crack propagation, as recognized by Kim.
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Regarding claim 2, Kang further teaches the first connection electrode comprising a first connection region connecting the (1-1)-th region and the (1-2)-th region, and wherein the (1-3)-th region protrudes from the first connection region (Figs. 11a and 12, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223).
Regarding claim 3, Kang further teaches the (1-2)-th region and the (1-3)-th region are spaced apart from each other (Figs. 11a and 12, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223).
Regarding claim 4, Kang further teaches the (1-2)-th region and the (1-3)-th region protrude in a first direction, and wherein the first connection region extends in a second direction that is substantially perpendicular to the first direction (Figs. 11A and 12, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223).
Regarding claim 5, Kang further teaches the third transistor comprises a first region, a second region, and a channel between the first region and the second region, and wherein the (1-2)-th region and the (1-3)-th region are electrically connected to the second region of the third transistor (Figs. 11A, 12, and 13, compensation thin-film transistor T3, compensation drain area D3, compensation channel area A3, compensation source area S3, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2; ¶131, 166, 214-223).
Regarding claim 6, Kang further teaches the (1-2)-th region and the (1-3)-th region are connected to the third transistor through an opening (Figs. 11A and 12, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223).
Regarding claim 7, Kang further teaches the (1-2)-th region and the (1-3)-th region are spaced apart from the second gate conductive layer and the third gate conductive layer (Figs. 11A and 12, second connection contact hole CNT1-2, second contact hole CNT2, second electrode CE2, first initialization gate electrode G4; ¶214-223).
Regarding claim 8, Kang further teaches the connection metal conductive layer further comprises a twelfth connection electrode that comprises a (2-1)-th region and a (2-2)-th region overlapping the second transistor, and that comprises a second connection region between the (2-1)-th region and the (2-2)-th region (Fig. 13, first connection electrode 167, upper connection electrode 177; ¶126, 194, 214-229).
Regarding claim 9, Kang further teaches the second transistor comprises a first region, a second region, and a channel between the first region and the second region, and wherein the (2-1)-th region and the (2-2) region overlap the second region of the second transistor (Fig. 13, light emission control source area S6, light emission control drain area D6, light emission control channel area A6, first connection electrode 167, upper connection electrode 177; ¶126, 159, 194, 214-229).
Regarding claim 10, Kang further teaches he (2-1)-th region and the (2-2)-th region are connected to the second region of the second transistor through an opening (Fig. 13, first connection electrode 167, upper connection electrode 177, light emission control drain area D6; ¶126, 159, 194, 214-229).
Regarding claim 11, Kang further teaches the second connection region being spaced apart from the second transistor (Fig. 13, first connection electrode 167, light emission control drain area D6; ¶126, 159, 194, 214-229).
Regarding claim 12, Kang further teaches the second transistor further comprising a protrusion overlapping the (2-1)-th region and the (2-2)-th region (Fig. 11A and 13, light emission control thin-film transistor T6, first connection electrode 167, upper connection electrode 177; ¶126, 159, 194, 214-229).
Regarding claim 13, Kang further teaches the connection metal conductive layer comprises at least one of gold (Au), silver (Ag), aluminum (Al), copper (Cu), platinum (Pt), and iron (Fe) (¶180).
Regarding claim 14, Kang further teaches a display device comprising: a substrate (Fig. 12, substrate 110; ¶152-156, 215); a first semiconductor layer above the substrate, and comprising a first transistor and a second transistor (Fig. 12, transistors T1, T2, T5, T6, T7; ¶118-119, 126, 215, 221); a first gate conductive layer and a second gate conductive layer above the first semiconductor layer (Fig. 12, driving gate electrode G1, second electrode CE2; ¶121-127, 164, 172, 215, 222); a second semiconductor layer above the second gate conductive layer, and comprising a third transistor that comprises a first region, a second region, and a channel (Fig. 12, transistors T3 & T4, compensation drain area D3, compensation source area S3, compensation channel area A3; ¶128-129, 131, 215, 218, 220); a third gate conductive layer above the second semiconductor layer (Fig. 12, compensation gate electrode G3, first initialization gate electrode G4; ¶131-133, 215); a connection metal conductive layer above the insulating film, and comprising a first connection electrode electrically connecting the first transistor to the third transistor, the first connection electrode comprising a (1-1)-th region overlapping the first transistor and a (1-2)-th region covering the second region of the third transistor (Figs. 11a and 12, first interlayer insulating layer 114, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2, compensation source area S3; ¶214-223); and a first data conductive layer and a second data conductive layer above the connection metal conductive layer (Fig. 12, data line DL, fire wire FL1′; ¶214-217, 225-229).
However, Kang does not explicitly teach an insulating film that comprises a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer.
Kim teaches an insulating film that comprises a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer (Figs. 4 and 5a, groove GR, organic filler 161; ¶85-87, 90-99, 141-145).
Kang and Kim are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the display device of Kang with the groove and organic filler of Kim such that an insulating film that comprises a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer. For the purpose of better protecting the device from damage such as external shocks and crack propagation, as recognized by Kim.
Regarding claim 15, Kang further teaches the first connection electrode comprising a first connection region connecting the (1-1)-th region and the (1-2)-th region, and extending in a first direction, and wherein the (1-2)-th region and the first connection region extend in a second direction that is substantially perpendicular to the first direction (Figs. 11a and 12, first intermediate connection electrode 155, node connection line 166, first connection contact hole CNT1-1, second connection contact hole CNT1-2, second contact hole CNT2; ¶214-223).
Regarding claim 16, Kang further teaches the third transistor comprising the channel between the first region and the second region, and wherein the (1-2)-th region is electrically connected to the second region of the third transistor through at least two openings (Figs. 11a and 12, node connection line 166, second connection contact hole CNT1-2, second contact hole CNT2, compensation source area S3; ¶214-223).
Regarding claim 17, Kang further teaches the (1-2)-th region being spaced apart from the second gate conductive layer and the third gate conductive layer (Figs. 11A and 12, second connection contact hole CNT1-2, second contact hole CNT2, second electrode CE2, first initialization gate electrode G4; ¶214-223).
Regarding claim 18, Kang further teaches the connection metal conductive layer further comprising a twelfth connection electrode that comprises a (2-1)-th region and a (2-2)-th region overlapping the second transistor, and a second connection region between the (2-1)-th region and the (2-2)-th region (Fig. 13, first connection electrode 167, upper connection electrode 177; ¶126, 194, 214-229).
Regarding claim 19, Kang further teaches the second transistor comprising a first region, a second region, and a channel between the first region and the second region, and wherein the (2-1)-th region and the (2-2)-th region are connected to the second region of the second transistor through an opening (Fig. 13, light emission control source area S6, light emission control drain area D6, light emission control channel area A6, first connection electrode 167, upper connection electrode 177; ¶126, 159, 194, 214-229).
Regarding claim 20, Kang further teaches the second connection region overlapping the second transistor (Fig. 13, light emission control source area S6, light emission control drain area D6, light emission control channel area A6, first connection electrode 167, upper connection electrode 177; ¶126, 159, 194, 214-229).
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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