DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/27/2023, 6/6/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 and 16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim (US 2018/0323170).
Regarding claim 10, Kim discloses, in at least figures 9A-9B and related text, a semiconductor device, comprising:
a substrate (910, [88]);
a bond pad (9122, [94]) formed on a front side (lower side of 910, figure) of the substrate (910, [88]) and extending to a position having a distance from a first lateral surface (left side surface of 910, figures) of the substrate (910, [88]);
an encapsulant layer (940, [95], [104]) supported on a back side (upper side of 910, figure) of the substrate (910, [88]); and
a shielding layer (960, [97]) formed on the back side (upper side of 910, figure) of the substrate (910, [88]), wherein the shieling layer (960, [97]) covers the encapsulant layer (940, [95], [104]).
Regarding claim 16, Kim discloses the semiconductor device of claim 10 as described above.
Kim further discloses, in at least figures 9A-9B and related text, one or more electronic components (920/9201/9202/931/932, [91]) encapsulated by the encapsulant layer (940, [95], [104]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haney (US 2017/0280561) in view of Kim (US 2018/0323170).
Regarding claim 1, Haney discloses, in at least figures 2A-2F and related text, a method for forming a shielding layer on a semiconductor device, wherein the semiconductor device comprises a bond pad (Cu layer for 121, [28], figures) formed on a front side (lower side of 115, figures) of a substrate (115, [17]) and extends to a first lateral surface (left side surface of 115, figures) of the substrate (115, [17]), the method comprising:
etching a portion of the bond pad (Cu layer for 121, [28], figures) adjacent to the first lateral surface (left side surface of 115, figures), to form a gap (lateral space between 121 and left side of 115, figures) between the bond pad (121, [28], figures) and the first lateral surface (left side surface of 115, figures); and
applying a shielding layer (180, [22]) to a back side (upper side of 115, figures) of the substrate (115, [17]).
Haney does not explicitly disclose attaching a filler onto the bond pad to fill the gap.
Kim teaches, in at least figures 9A-9B and related text, the method comprising attaching a filler (950 in 985, [96]) onto the bond pad (9122, [94]) to fill the gap (lateral space between 9122 and left side surface of 910, [94], figures), for the purpose of preventing warpage by forming a molding on both surfaces of a substrate and providing shield electromagnetic interference (EMI) by an EMI shielding layer formed to cover the molding and the substrate ([41]).
Haney and Kim are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haney with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Haney to have the attaching a filler onto the bond pad to fill the gap, as taught by Kim, for the purpose of preventing warpage by forming a molding on both surfaces of a substrate and providing shield electromagnetic interference (EMI) by an EMI shielding layer formed to cover the molding and the substrate ([41], Kim).
Regarding claim 2, Haney in view of Kim discloses the method of claim 1 as described above.
Kim further teaches, in at least figures 9A-9B and related text, a dielectric layer (950 in right side of 980, [95], [104], figures) formed on the front side (lower side of 910, figures) of the substrate (910, [94]), the dielectric layer (950 in right side of 980, [95], [104], figures) extending from the bond pad (9122, [94]) to a second lateral surface (right side surface of 910, figures) of the substrate (910, [94]) opposite to the first lateral surface (left side surface of 910, figures), and wherein attaching a filler onto the bond pad to fill the gap further comprises: attaching the filler (950 in 985, [96]) that substantially flushes with the dielectric layer (950 in right side of 980, [95], [104], figures) to form a flat surface (figures), for the purpose of preventing warpage by forming a molding on both surfaces of a substrate and providing shield electromagnetic interference (EMI) by an EMI shielding layer formed to cover the molding and the substrate ([41]).
Regarding claim 5, Haney in view of Kim discloses the method of claim 1 as described above.
Kim further teaches, in at least figures 9A-9B and related text, the filler (950 in 985, [95], [96]) includes an epoxy material ([104]), for the purpose of preventing warpage by forming a molding on both surfaces of a substrate and providing shield electromagnetic interference (EMI) by an EMI shielding layer formed to cover the molding and the substrate ([41]).
Regarding claim 7, Haney in view of Kim discloses the method of claim 1 as described above.
Haney further discloses, in at least figures 2A-2F and related text, one or more electronic components (161/162/163, [19]) supported on the back side (upper side of 115, figures) of the substrate (115, [17]), and wherein the shielding layer (180, [22]) covers the one or more electronic components (161/162/163, [19]).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haney (US 2017/0280561) in view of Kim (US 2018/0323170), and further in view of Chen (US 9,627,228).
Regarding claim 3, Haney in view of Kim discloses the method of claim 1 as described above.
Haney in view of Kim does not explicitly disclose the filler is a tape which includes a first portion filling the gap and a second portion attached onto and covering the bond pad.
Chen teaches, in at least figures 1A-1E and related text, the method comprising the filler (110/140, col. 4/ line 27- col. 6/ line 40) is a tape which includes a first portion filling the gap (lateral space between pad for 124 and left side surface of 126, col. 4/ line 27- col. 6/ line 40, figures) and a second portion attached onto and covering the bond pad (pad for 124, col. 4/ line 27- col. 6/ line 40, figures), for the purpose of providing terminal protection film on the chip package structure for protecting terminals (e.g., tin solder balls, bumps) of the chip package structure from effects of a high temperature process (col. 1/ line 65- col. 2/ line 29).
Haney, Kim, and Chen are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haney in view of Kim with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Haney in view of Kim to have the filler being a tape which includes a first portion filling the gap and a second portion attached onto and covering the bond pad, as taught by Chen, for the purpose of providing terminal protection film on the chip package structure for protecting terminals (e.g., tin solder balls, bumps) of the chip package structure from effects of a high temperature process (col. 1/ line 65- col. 2/ line 29, Chen).
Regarding claim 4, Haney in view of Kim discloses the method of claim 3 as described above.
Chen further teaches, in at least figures 1A-1E and related text, detaching the tape (110/140, col. 4/ line 27- col. 6/ line 40) from the bond pad (pad for 124, col. 4/ line 27- col. 6/ line 40, figures), for the purpose of providing terminal protection film on the chip package structure for protecting terminals (e.g., tin solder balls, bumps) of the chip package structure from effects of a high temperature process (col. 1/ line 65- col. 2/ line 29).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haney (US 2017/0280561) in view of Kim (US 2018/0323170), and further in view of Heppner (US 2018/0166363).
Regarding claim 6, Haney in view of Kim discloses the method of claim 5 as described above.
Haney in view of Kim does not explicitly disclose dispensing the epoxy material into the gap.
Heppner teaches, in at least figures 1A-1D and related text, the method comprising dispensing the epoxy material (130, [31]) into the gap (lateral space between 105 and left side surface of 103, [27], [28]), for the purpose of providing EMI shielding on semiconductor packages with minimal footprint ([21]).
Haney, Kim, and Heppner are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haney in view of Kim with the specified features of Heppner because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Haney in view of Kim to have the dispensing the epoxy material into the gap, as taught by Heppner, for the purpose of providing EMI shielding on semiconductor packages with minimal footprint ([21], Heppner).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 9,793,222) in view of Haney (US 2017/0280561).
Regarding claim 8, Lee discloses, in at least figures 1-3, 16-21, 28-31, and related text, a method for forming a semiconductor device, the method comprising:
providing a substrate strip (200, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) having a device array (array of 120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) with a plurality of device regions (101 of 120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) defined by a plurality of saw streets (region of 200 in between 101 and 101, figures), wherein the plurality of device regions (101 of 120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) is connected together by a wiring grid (grid of 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) formed on a front surface (lower surface of 200, figures) of the substrate strip (200, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42);
singulating at the saw streets (region of 200 in between 101 and 101, figures) the substrate strip (200, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) to form a plurality of semiconductor devices (120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) each corresponding to one of the plurality device regions (101 of 120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42), wherein each semiconductor device (120/122, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) has a substrate (102, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) and a bond pad (leftmost 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) which is a part of the wiring grid (grid of 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42);
attaching a filler (300, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) onto the bond pad (leftmost 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) to fill the gap (lateral space between 110 and left side surface of 102, figures); and
applying a shielding layer (150, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) to a back side (upper side of 102, figures) of the substrate (102, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42).
the bond pad is formed on a front side of the substrate and extending to a first lateral surface of the substrate; etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface.
Lee does not explicitly disclose the bond pad is formed on a front side of the substrate and extending to a first lateral surface of the substrate; etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface.
Haney teaches, in at least figures 2A-2F and related text, the method comprising the bond pad (Cu layer for 121, [28], figures) is formed on a front side (lower side of 115, figures) of the substrate (115, [17]) and extending to a first lateral surface (left side surface of 115, figures) of the substrate (115, [17]); etching a portion of the bond pad (Cu layer for 121, [28], figures) adjacent to the first lateral surface (left side surface of 115, figures), to form a gap (lateral space between 121 and left side of 115, figures) between the bond pad (121, [28], figures) and the first lateral surface (left side surface of 115, figures), for the purpose of preventing the external shield from interconnecting with or otherwise contacting the pins or contact pads thereby achieving a high quality conformal external shield, with a reduced error rate of undesired electrical connections caused by spillover ([14]).
Lee and Haney are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Haney because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Lee to have the bond pad being formed on a front side of the substrate and extending to a first lateral surface of the substrate; the etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface, as taught by Haney, for the purpose of preventing the external shield from interconnecting with or otherwise contacting the pins or contact pads thereby achieving a high quality conformal external shield, with a reduced error rate of undesired electrical connections caused by spillover ([14], Haney).
Regarding claim 9, Lee in view of Haney discloses the method of claim 9 as described above.
Haney further teaches, in at least figures 2A-2F and related text, a semiconductor device manufactured (100, [19]) by the method of claim 8, for the purpose of preventing the external shield from interconnecting with or otherwise contacting the pins or contact pads thereby achieving a high quality conformal external shield, with a reduced error rate of undesired electrical connections caused by spillover ([14]).
Claim(s) 11-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0323170) in view of Haney (US 2017/0280561).
Regarding claim 16, Kim discloses the semiconductor device of claim 10 as described above.
The claimed limitation of "the bond pad and the shielding layer are formed by the following steps: forming a bond pad that extends to the first lateral surface; etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface; attaching a filler onto the bond pad to fill the gap; and applying the shielding layer onto the back side of the substrate" has not patentable weight because it is interpreted as product-by-process.
Kim further discloses, in at least figures 9A-9B and related text, the bond pad (9122, [94]) and the shielding layer (960, [97]) are formed by the following steps:
attaching a filler (950 in 985, [96]) onto the bond pad (9122, [94]) to fill the gap (lateral space between 9122 and left side surface of 910, [94], figures); and
applying the shielding layer (960, [97]) onto the back side (upper side of 910, figure) of the substrate (910, [88]).
Kim does not explicitly disclose forming a bond pad that extends to the first lateral surface; etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface.
Haney teaches, in at least figures 2A-2F and related text, the device comprising forming a bond pad (Cu layer for 121, [28], figures) that extends to the first lateral surface (left side surface of 115, figures); etching a portion of the bond pad (Cu layer for 121, [28], figures) adjacent to the first lateral surface (left side surface of 115, figures), to form a gap (lateral space between 121 and left side of 115, figures) between the bond pad (121, [28], figures) and the first lateral surface (left side surface of 115, figures), for the purpose of preventing the external shield from interconnecting with or otherwise contacting the pins or contact pads thereby achieving a high quality conformal external shield, with a reduced error rate of undesired electrical connections caused by spillover ([14]).
Kim and Haney are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim with the specified features of Haney because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Kim to have the forming a bond pad that extends to the first lateral surface; the etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface, as taught by Haney, for the purpose of preventing the external shield from interconnecting with or otherwise contacting the pins or contact pads thereby achieving a high quality conformal external shield, with a reduced error rate of undesired electrical connections caused by spillover ([14], Haney).
Regarding claim 12, Kim in view of Haney discloses the semiconductor device of claim 11 as described above.
Kim further discloses, in at least figures 9A-9B and related text, a dielectric layer (950 in right side of 980, [95], [104], figures) formed on the front side (lower side of 910, figures) of the substrate (910, [94]), the dielectric layer (950 in right side of 980, [95], [104], figures) extending from the bond pad (9122, [94]) to a second lateral surface (right side surface of 910, figures) of the substrate (910, [94]) opposite to the first lateral surface (left side surface of 910, figures), wherein the filler (950 in 985, [96]) and the dielectric layer (950 in right side of 980, [95], [104], figures) are substantially flush with each other to form a flat surface (figures).
Regarding claim 15, Kim in view of Haney discloses the semiconductor device of claim 11 as described above.
Kim further discloses, in at least figures 9A-9B and related text, the filler (950 in 985, [95], [96]) includes an epoxy material ([104]).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0323170) in view of Haney (US 2017/0280561), and further in view of Lee (US 9,793,222).
Regarding claim 13, Kim in view of Haney discloses the semiconductor device of claim 11 as described above.
Kim in view of Haney does not explicitly disclose the filler is a tape which includes a first portion filling the gap and a second portion attached onto and covering the bond pad.
Lee teaches, in at least figures 1-3, 16-21, 28-31, and related text, the device comprising the filler (300, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) is a tape (col. 11/ line 61-col. 12/ line 42) which includes a first portion filling the gap (lateral space between 110 and left side surface of 102, figures) and a second portion attached onto and covering the bond pad (leftmost 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42), for the purpose of providing electrically conductive shield layer (e.g. EMI shielding layer) on the top and side surfaces of the molding compound, and in physical contact with the surface of the exposed electrically conductive ground structure thereby preventing failure of shielding effect by defective electrical connection (col. 1/ lines 23-54).
Kim, Haney and Lee are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Haney with the specified features of Lee because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Kim in view of Haney to have the filler being a tape which includes a first portion filling the gap and a second portion attached onto and covering the bond pad, as taught by Lee, for the purpose of providing electrically conductive shield layer (e.g. EMI shielding layer) on the top and side surfaces of the molding compound, and in physical contact with the surface of the exposed electrically conductive ground structure thereby preventing failure of shielding effect by defective electrical connection (col. 1/ lines 23-54, Lee).
Regarding claim 14, Kim in view of Haney and Lee discloses the semiconductor device of claim 13 as described above.
Lee further teaches, in at least figures 1-3, 16-21, 28-31, and related text, the tape (300, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) is detached from the bond pad (leftmost 110, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) after applying the shielding layer (150, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42) to the back side (upper side of 102, figures) of the substrate (102, col. 9/ line 55-col. 10/ line 58, col. 11/ line 61-col. 12/ line 42), for the purpose of providing electrically conductive shield layer (e.g. EMI shielding layer) on the top and side surfaces of the molding compound, and in physical contact with the surface of the exposed electrically conductive ground structure thereby preventing failure of shielding effect by defective electrical connection (col. 1/ lines 23-54).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811