CTNF 18/475,292 CTNF 91257 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Invention I, Species F (reading on claims 1-3, 5-11, 13-17 and new claims 21-25) in the reply filed on 04/14/2026 is acknowledged. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 10, 14, 21, 22 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (US 20220278065 A1; hereinafter “Lee”) . In re claim 1, Lee discloses in figs. 3A-3G, fig. 6A, a semiconductor package comprising: a package substrate 270 comprising a top surface that extends in a horizontal direction (fig. 3G; ¶34); an interposer 210 bonded to the top surface of the package substrate 270 (¶34); a semiconductor die 100 bonded to a top surface of the interposer 210 (¶34), the semiconductor die 100 comprising: a bottom surface FS (¶38) that faces the top surface of the interposer 210 ; and chamfers CE (fig. 6A; ¶18) formed in corners of the bottom surface of the semiconductor die FS , wherein the chamfers include chamfered surfaces SS1, SS2, SS3 (fig. 6A; ¶39); and a molding layer 240a surrounding the semiconductor die 100 and contacting the chamfered surfaces SS1, SS2, SS3 (fig. 6A; ¶34). In re claim 2, Lee discloses in figs. 3A-3G, fig. 6A, the semiconductor package of claim 1, wherein the chamfered surfaces comprise: an upper surface RS that faces the interposer 210 ; and a side surface (SS1, SS2, SS3) that extends from the upper surface to the bottom surface of the semiconductor die FS . In re claim 3, Lee discloses in figs. 3A-3G, fig. 6A, the semiconductor package of claim 2, wherein the side surface (SS1, SS2, SS3) extends between adjoining first and second sidewalls of the semiconductor die (fig. 6A; vertical and horizontal sidewalls of the die 100). In re claim 10 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 2, wherein a minimum horizontal distance between a perpendicular corner of the upper surface and the side surface is less than 5000 microns (μm) (Lee discloses referring to FIG. 6A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers; ¶48). In re claim 14, Lee discloses in figs. 3A-3G, fig. 6A, a semiconductor package comprising: a package substrate 270 comprising a top surface that extends in a horizontal direction (fig. 3G; ¶34); an interposer 210 bonded to the top surface of the package substrate 270 (¶34); a semiconductor die 100 disposed on the interposer 210 (¶34), the semiconductor die 100 comprising: a bottom surface FS (¶38) that faces a top surface of the interposer 210 ; and chamfers CE (fig. 6A; ¶18) formed in corners of the bottom surface of the semiconductor die FS , a bonding layer (a bonding layer comprising 124, 214c) (¶16, 28) bonding the semiconductor die 100 to the interposer; and a molding layer 240a surrounding the semiconductor die 100 and contacting the chamfered surfaces SS1, SS2, SS3 (fig. 6A; ¶34). a molding layer 240, 230 disposed on the bonding layer (124, 214c) and surrounding the semiconductor die 100 , the molding layer 240, 230 (¶34) extending between the semiconductor die 100 and the interposer 210 and contacting the chamfers CE . In re claim 21, Lee discloses in figs. 3A-3G, fig. 6A, a semiconductor package comprising: an interposer 210 (¶24); a semiconductor die 100 bonded to a top surface of the interposer by a bonding layer (a bonding layer comprising 124, 214c) (¶16, 28), the semiconductor die comprising: a bottom surface FS (¶38) that faces a top surface of the interposer 210 ; and chamfers CE (fig. 6A; ¶18) formed in corners of the bottom surface of the semiconductor die FS , wherein the chamfers CE include chamfered surfaces SS1, SS2, SS3 (fig. 6A; ¶39); and a molding layer 240a surrounding the semiconductor die 100 and contacting the chamfered surfaces SS1, SS2, SS3, RS (fig. 6A; ¶34). In re claim 22, Lee discloses in figs. 3A-3G, fig. 6A, the semiconductor package of claim 21, wherein the chamfered surfaces comprise: an upper surface RS that faces the interposer 210 ; and a side surface (SS1, SS2, SS3) that extends from the upper surface to the bottom surface of the semiconductor die FS and between adjoining first and second sidewalls of the semiconductor die 100 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 5-9, 11, 15-17, 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220278065 A1; hereinafter “Lee”) . In re claims 5 and 23, Lee discloses in figs. 3A-3G, fig. 6A, the semiconductor package, wherein the side surface comprises: a first side surface SS1 that defines a first vertically aligned plane (¶39-40); and a second side surface SS2 that defines a second vertically aligned plane (¶39-40), wherein an internal angle formed between the first side surface and the second side surface is more than 95 0 , less than 180 0 (based on fig. 6A and the angle θ 2 cited in ¶48), which overlaps the claimed range of 179° to 100°. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee to form the side surface of the chamfered corners having an obtuse angle with the claimed range in order to reduce warpage of the semiconductor package (¶1 of Lee). In re claim 6 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 5. Lee does not expressly disclose wherein an area of the first side surface is greater than an area of the second side surface. However, it has been held to be within the general skill of a worker in the art to select areas of the first and second surface at the chamfered corner on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied , 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select an area of the first side surface is greater than an area of the second side surface in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 7 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 5. Lee does not expressly disclose wherein an area of the first side surface is equal to an area of the second side surface. However, it has been held to be within the general skill of a worker in the art to select areas of the first and second surface at the chamfered corner on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied , 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select an area of the first side surface is equal to an area of the second side surface in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 8, same as claims 22 and 23 above. In re claim 9 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 2. Lee further discloses referring to FIG. 6A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers (¶48). Lee does not expressly disclose wherein a vertical depth of each chamfer ranges from 0.5% to 75% of a thickness of the semiconductor die. However, it has been held to be within the general skill of a worker in the art to select a height of the chamfer as the claimed range on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied , 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a height of the chamfer as the claimed range in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 11 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 10, wherein a minimum horizontal distance ranges from 5 μm to 500 μm (¶48), which overlaps the claimed ranges from 100 μm to 5000 μm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and arrived at the claimed ranges for the minimum horizontal distance in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. In re claim 15 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 14, wherein: the semiconductor die 100 has a semiconductor die width, a semiconductor die length, and a semiconductor die thickness (the semiconductor die 100 inherently has a semiconductor die width, a semiconductor die length, and a semiconductor die thickness). Lee further discloses referring to FIG. 6A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers (¶48). Lee does not expressly disclose wherein a vertical depth of each chamfer ranges from 0.5% to 75% of the semiconductor die thickness; a length of each chamfer ranges from 0.5% to 50% of the semiconductor die length; and a width of each chamfer ranges from 0.5% to 50% of the semiconductor die width. However, it has been held to be within the general skill of a worker in the art to select a depth, length and width of the chamfer relative to the dimensions of the semiconductor die as the claimed range on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied , 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a depth, length and width of the chamfer relative to the dimensions of the semiconductor die in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 16 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 15. . Lee further discloses referring to FIG. 6A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers (¶48). Lee does not expressly disclose vertical depth of each chamfer ranges from 0.5% to 20% of the semiconductor die thickness; the length of each chamfer ranges from 0.5% to 5% of the semiconductor die length; and the width of each chamfer ranges from 0.5% to 5% of the semiconductor die width. However, it has been held to be within the general skill of a worker in the art to select a depth, length and width of the chamfer relative to the dimensions of the semiconductor die as the claimed range on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied , 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a depth, length and width of the chamfer relative to the dimensions of the semiconductor die in order to control the bonding of the semiconductor die with the surrounding encapsulation materials and to control warpage issues of the packaging process. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 17, same as claim 5 above. In re claim 24, Lee discloses in figs. 3A-3G, fig. 6A, the semiconductor package of claim 23, wherein: the side surface further comprises a third side surface SS3 that defines a third vertically aligned plane; and an internal angle formed between the second side surface SS2 and the third side surface SS3 is more than 95 0 , less than 180 0 (based on fig. 6A and the angle θ 3 cited in ¶48), which overlaps the claimed range of 179° to 100°. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee to form the side surface of the chamfered corners having an obtuse angle with the claimed range in order to reduce warpage of the semiconductor package (¶1 of Lee). In re claim 25, same as claims 6 and 7 above . 07-22-aia AIA Claim (s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220278065 A1; hereinafter “Lee”) , as applied to claim 1 above and further in view of Kim et al. (US 20240120263 A1; hereinafter “Kim”) . In re claim 13 , Lee discloses in figs. 1-3, 6A, the semiconductor package of claim 1, further comprising: at least one peripheral die 220 disposed around the semiconductor die 100 and bonded to the package substrate 270 (¶29). Lee does not expressly disclose more than one peripheral dies and a package ring disposed on a perimeter of the package substrate surrounding the semiconductor die and the peripheral dies; and a cover disposed on the package ring. In the same field of endeavor, Kim discloses in fig. 25, a semiconductor package, comprising: plurality of peripheral dies 400 disposed around a semiconductor die 300 (¶22), and a package ring 650 disposed on a perimeter of the package substrate 100 surrounding the semiconductor die 300 and the peripheral dies 400 (¶58-59); and a cover 720 disposed on the package ring 650 (¶134). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Kim into the package of Lee to enhance performance of the chip package and also to prevent warpage of the package substrate (¶59 of Kim). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NILUFA RAHIM/Primary Examiner, Art Unit 2893 Application/Control Number: 18/475,292 Page 2 Art Unit: 2893 Application/Control Number: 18/475,292 Page 3 Art Unit: 2893 Application/Control Number: 18/475,292 Page 4 Art Unit: 2893 Application/Control Number: 18/475,292 Page 5 Art Unit: 2893 Application/Control Number: 18/475,292 Page 6 Art Unit: 2893 Application/Control Number: 18/475,292 Page 7 Art Unit: 2893 Application/Control Number: 18/475,292 Page 8 Art Unit: 2893 Application/Control Number: 18/475,292 Page 9 Art Unit: 2893 Application/Control Number: 18/475,292 Page 10 Art Unit: 2893 Application/Control Number: 18/475,292 Page 11 Art Unit: 2893 Application/Control Number: 18/475,292 Page 12 Art Unit: 2893 Application/Control Number: 18/475,292 Page 13 Art Unit: 2893 Application/Control Number: 18/475,292 Page 14 Art Unit: 2893 Application/Control Number: 18/475,292 Page 15 Art Unit: 2893
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