Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 06/10/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-12, 14-15, 20-21, 23-25, 41.
Examiner acknowledges the amendments added into the specification.
Response to Arguments
Applicant's arguments filed 06/10/2026 have been fully considered but they are not persuasive.
Applicant asserts regarding independent claim 1:
The Office Action alleges that Koyama, under two separate interpretations, discloses
each and every limitation of independent claim 1. Office Action, pp. 3, 6-7. In its first rejection, the Office Action alleges that the gate trench 6 and termination trench 7 of Koyama correspond to the claimed "first portion" and "second portion," respectively. Office Action, p. 3. In its second rejection (i.e., "alternative interpretation"), the Office Action alleges that the termination trench 7 and the gate trench 6 of Koyama correspond to the claimed "first portion" and "second portion," respectively. Office Action, pp. 6-7. Even assuming arguendo that the trenches 6, 7 of Koyama are similar to the claimed "first portion" and "second portion," neither the termination trench 7 nor the gate trench 6 of Koyama have a "second width at a first point in the second portion [that] is different from the second width at a second point in the second portion" as recited in amended claim 1. As such, amended claim 1 is patentable over Koyama under both interpretations set forth in the Office Action.
Examiner’s response:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The claim amendment (“wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion”) necessitated new search and Nishi et al. (US 20220013437 A1) has been applied in the current rejection to teach the amended claim limitation, as describe below in both 102 and 103 section.
Applicant asserts regarding independent claim 1:
The Office Action further alleges that Matsuura discloses each and every limitation of independent claim 1. Office Action, pp. 7-8. In its rejection, the Office Action alleges that gate trench 11 and peripheral gate trench 111 of Matsuura correspond to the claimed "first portion" and "second portion," respectively. Office Action, pp. 7-8. However, like Koyama, the peripheral gate trench 111 of Matsuura does not have a "second width at a first point in the second portion [that] is different from the second width at a second point in the second portion" as recited in amended claim 1. As such, amended claim 1 is patentable over Matsuura.
Examiner’s response:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant asserts regarding independent claim 25:
The Office Action alleges that Koyama discloses each and every limitation of
independent claim 25. Office Action, p. 5. In its rejection, the Office Action alleges that the first gate electrode 9 and field dielectric film 10 of Koyama correspond to the claimed "gate finger" and "field insulating layer," respectively. Id. The Office Action further alleges that the termination trench 7 of Koyama corresponds to the claimed "second portion" of the claimed "gate trench." Id. Even assuming arguendo that the first gate electrode 9 and field dielectric film 10 of Koyama are similar to the claimed "gate finger" and "field insulating layer" as alleged in the Office Action, the first gate electrode 9 (i.e., alleged "gate finger") does not "extend over" the field dielectric film 10 (i.e., alleged "field insulating layer") "in the second portion of the gate trench" as recited in amended claim 25. As such, amended claim 25 is patentable over Koyama.
The additional references cited in the Office Action fail to cure the aforementioned deficiencies of Koyama. Thus, for at least these reasons, Applicant respectfully submits the cited references, taken alone and/or in combination, fail to disclose each and every limitation of independent claim 25 as amended herein. Accordingly, withdrawal of the standing rejections under 35 U.S.C. § 102 as applied to amended claim 25 and allowance of amended claim 25 is respectfully requested.
Examiner’s response:
Applicant’s arguments with respect to claim(s) 25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The claim amendment (“wherein the gate finger extends over the field insulating layer in the second portion of the gate trench”) necessitated further consideration and has been rejected over Koyama in view of Matsuura, as describe below the 103 section.
Applicant asserts regarding independent claim 41:
The Office Action alleges that Koyama discloses each and every limitation of
independent claim 41. Office Action, p. 6. In its rejection, the Office Action alleges that the first gate electrode 9 and field dielectric film 10 of Koyama correspond to the claimed "gate finger" and "field insulating layer," respectively. Office Action, p. 6. Even assuming arguendo that the first gate electrode 9 and field dielectric film 10 of Koyama are similar to the claimed "gate finger" and "field insulating layer," the field dielectric film 10 (i.e., alleged "field insulating layer") is formed on top of first gate electrode 9 (i.e., alleged "gate finger") such that the first gate electrode 9 is between the field dielectric film 10 and the alleged wide bandgap semiconductor structure. Hence, Koyama fails to disclose or suggest "a field insulating layer in the second portion of the gate trench between the gate finger and the wide bandgap semiconductor structure" as recited in amended claim 41. (Emphasis added). As such, amended claim 41 is patentable over Koyama.
The additional references cited in the Office Action fail to cure the aforementioned deficiencies of Koyama. Thus, for at least these reasons, Applicant respectfully submits the cited references, taken alone and/or in combination, fail to disclose each and every limitation of independent claim 41 as amended herein. Accordingly, withdrawal of the standing rejections under 35 U.S.C. § 102 as applied to amended claim 41 and allowance of amended claim 41 is respectfully requested.
Examiner’s response:
Applicant’s arguments with respect to claim(s) 41 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The claim amendment (“the field insulating layer is between the gate finger and the wide bandgap semiconductor structure”) necessitated further consideration and has been rejected over Koyama in view of Matsuura, as describe below the 103 section.
Therefore, the rejections stand.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “The semiconductor device of claim 1, wherein the second width is greater than the first width”. Claim 2 depends on claim 1 and claim 1 has been amended further narrowing the second width, e.g., wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion. Thus, it is unclear is the second width cited in claim 2 is referring to the second width at a first point or a second point. For examination purpose, this will be interpreted as either a second width at a first point or second point.
Claim 3 recites “The semiconductor device of claim 1, wherein the second width is less than the first width”. Claim 3 depends on claim 1 and claim 1 has been amended further narrowing the second width, e.g., wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion. Thus, it is unclear is the second width cited in claim 3 is referring to the second width at a first point or a second point. For examination purpose, this will be interpreted as either a second width at a first point or second point.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishi et al. (US 20220013437 A1; hereinafter “Nishi”).
In re claim 1, Nishi discloses in figs. 1-6, a semiconductor device, comprising:
a semiconductor structure 10 (¶25-27);
a gate finger 22 in a gate trench 20 in the semiconductor structure 10 (¶34-35); and
wherein the gate trench 20 extends a length in the semiconductor structure 10 (fig. 6),
the gate trench 20 having a first portion having a first width (e.g., a portion of the gate trench 20 in the active region; hereinafter “Trn1”; Trn1 has a width W11) and a second portion having a second width (e.g., a portion of the gate trench 20 in the wiring region; hereinafter “Trn2”; Trn2 has varying widths including W12), wherein the second width (e.g., W12) is different than the first width (e.g., W11) (¶53),
wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion (e.g., a width in the second portion at the transition region is different from a width on the right of the transition region in fig. 6).
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishi et al. (US 20220013437 A1; hereinafter “Nishi”), in an alternative interpretation.
In re claim 1, Nishi discloses in figs. 1-6, a semiconductor device, comprising:
a semiconductor structure 10 (¶25-27);
a gate finger 22 in a gate trench 20 in the semiconductor structure 10 (¶34-35); and
wherein the gate trench 20 extends a length in the semiconductor structure 10 (fig. 6),
the gate trench 20 having a first portion having a first width (e.g., a portion of the gate trench 20 in the wiring region; hereinafter “Trn1”; Trn1 has a width W12) and a second portion having a second width (e.g., a portion of the gate trench 20 in the transition region and active region; hereinafter “Trn2”; Trn2 has varying widths including W11), wherein the second width (e.g., W11) is different than the first width (e.g., W12) (¶53),
wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion (e.g., a width in the second portion at the active region is different from a width in the right of the transition region in fig. 6).
In re claim 3, Nishi discloses in figs. 1-6, the semiconductor device of claim 1, wherein the second width (e.g., W11) is less than the first width (e.g., W12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-9, 14-15, 21, 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama et al. (US 20250185285 A1; hereinafter “Koyama”) in view of Nishi et al. (US 20220013437 A1; hereinafter “Nishi”).
In re claim 1, Koyama discloses in figs. 1, 10 a semiconductor device (¶25), comprising:
a semiconductor structure (40, 50) (Applicant’s definition of the semiconductor structure, “[0051] As is shown in FIG. 2B, the power semiconductor device 100 includes a semiconductor structure that includes an active region 102 and an inactive region 104”. Koyama discloses “the semiconductor device includes an active region 40, which is a region in which a main current flows when the semiconductor device is in an operating state, and a termination region 50, which is a region outside the active region 40” including a semiconductor substrate 1; fig. 1, ¶25);
a gate finger 9 in a gate trench (6, 7) in the semiconductor structure (40, 50) (fig. 1, ¶26); and
wherein the gate trench (6, 7) extends a length in the semiconductor structure (in fig. 10, gate trench 6, 7 extends a length in a direction perpendicular to a 2D surface, that is into the page),
the gate trench (6, 7) having a first portion 6 having a first width and a second portion 7 having a second width, wherein the second width is different than the first width (¶37; “The termination trench 7 is an excavation that is connected to the gate trench 6 in a plan view, with its width in the extension direction of the gate trench 6 wider than the width of the gate trench 6”).
Koyama does not expressly disclose wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion.
In the same field of endeavor, Nishi discloses in figs. 1-6, a semiconductor device, comprising: a gate trench 20 having a first portion having a first width (e.g., a portion of the gate trench 20 in the active region; hereinafter “Trn1”; Trn1 has a width W11) and a second portion having a second width (e.g., a portion of the gate trench 20 in the wiring region; hereinafter “Trn2”; Trn2 has varying widths including W12), wherein the second width (e.g., W12) is different than the first width (e.g., W11) (¶53),
wherein the second width at a first point in the second portion is different from the second width at a second point in the second portion (e.g., a width in the second portion at the transition region is different from a width on the right of the transition region in fig. 6).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the second width of the gate trench of Koyama having two different widths as taught by Nishi.
One would have been motivated to do so as Nishi discloses having the spread angle, A1, of less than 45 degrees makes the spreading of the trench width gradual in the transition region. In other words, no significantly widened portion in trench width appears. Therefore, a shape of the trench having a significant change in the trench depth due to the micro-loading effect is not formed. The change of the depth of the trench is gradual. The formation of a level difference at the bottom portion of the trench is prevented. Therefore, the reliability of the gate insulating film 21 at the bottom portion of the trench improves (¶56-59 of Nishi).
In re claim 2, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, wherein the second width is greater than the first width (¶37).
In re claim 4, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 1, wherein the second portion 7 has a different shape relative to the first portion 6.
In re claim 6, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 1, wherein the second portion of the gate trench 7 is contiguous with an adjacent gate trench 6.
In re claim 7, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor device further comprises a gate bus 13, wherein the gate bus 13 overlaps at least a portion of the gate finger 9 in the second portion of the gate trench 7 (fig. 2; ¶26; the gate lead-out portion of the gate bus 13 overlaps the gate finger 9 in the second portion of the gate trench 7).
In re claim 8, Koyama as modified by Nishi discloses the semiconductor device of claim 7 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 7, wherein the gate finger 9 and the gate bus 13 extend in different directions (e.g., in fig.1, and gate fingers in the trench 6 extend in East-West direction and a portion of the gate bus 13 extends in North-South direction).
In re claim 9, Koyama as modified by Nishi discloses the semiconductor device of claim 7 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 7, further comprising a field insulating layer 10 between the gate bus 13 and the semiconductor structure 1 (¶86).
In re claim 14, Koyama as modified by Nishi discloses the semiconductor device of claim 9 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 9, wherein the field insulating layer 10 is in the second portion of the gate trench 7.
In re claim 15, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 14, wherein the field insulating layer 10 has a first thickness on a bottom surface of the gate trench 7 (a first thickness of the field insulating layer 10 below the top corner 7a) and a second thickness on a sidewall of the gate trench (i.e., the horizontal portion of the field insulating layer 10 underneath the second gate electrode outer periphery 13b), the first thickness being different than the second thickness.
In re claim 21, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor structure is a wide bandgap semiconductor structure (the MOSFET is a silicon carbide based MOSFET; ¶24, 30. Thus, the semiconductor structure is a wide bandgap semiconductor structure).
In re claim 23, Koyama as modified by Nishi discloses the semiconductor device of claim 21 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 21, wherein the wide bandgap semiconductor structure comprises silicon carbide (¶24, 30).
In re claim 24, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama further discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor device is a MOSFET (¶35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama as applied to claims 1 and 9 above, respectively.
In re claim 5, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama discloses in fig. 10, wherein the first portion 6 has a first length, the second portion 7 has a second length. Koyama does not expressly disclose wherein the first length is at least 10 times greater than the second length.
Koyama discloses a plurality of the strip shaped trenches 6 in the first portion and a single outer trench 7 in the second portion. Therefore, the first portion 6 has a first length which is a summation of all the strip shaped trenches 6. Koyama further discloses the strips of the gate trench 6 improve the performance of the semiconductor device (¶35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to make the first length of the first portion of the trenches 6 at least 10 times greater than the second length of the second portion of the trench 7 to improve the performance of the semiconductor device (¶35).
Moreover, it has been held to be within the general skill of a worker in the art to select a total gate length in the active region compared to the length of the gate runner in the peripheral region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a total gate length in the active region at least 10 times greater than the second length in the peripheral region in order to improve the performance of the semiconductor device.
In re claim 10, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama discloses in fig. 10, the semiconductor device of claim 9, wherein the field insulating layer 10 has a thickness between 0.1 μm and 5.0 μm (¶42), which encompasses the claimed range of about 0.3 microns to about to about 0.5 microns.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to form a thickness of the field insulating layer range of about 0.3 microns to about to about 0.5 microns to reducing the electric field applied to the gate dielectric film 8 provided in the vicinity of the termination trench top corner 7a and in suppressing the destruction of the gate dielectric film 8 (¶43).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama in view of Nishi, as applied to claim 10 above and further in view of Matsuura et al. (US 20090200607 A1; hereinafter “Matsuura”).
In re claim 11, Koyama as modified by Nishi discloses the semiconductor device of claim 10 outlined above, but does not expressly disclose the semiconductor device further comprising a gate oxide layer between the field insulating layer and the gate bus.
In the same field of endeavor, Matsuura discloses in figs. 1-3, a semiconductor device comprising a gate oxide layer 13 between the field insulating layer 17 and the gate bus 115 (¶65).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Matsuura into the device of Koyama in order to have a conformally formed gate oxide layer in the cell region and also in the peripheral region and isolate gate electrode from the substrate.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama in view of Nishi and Matsuura, as applied to claim 11 above and further in view of Losee et al. (US 20150155355 A1; hereinafter “Losee”).
In re claim 12, Koyama, as modified by, Nishi and Matsuura disclose the semiconductor device of claim 10 outlined above.
Matsuura does not expressly disclose wherein the gate oxide layer has a thickness of about 50 nm to about 100 nm.
Koyama discloses in fig. 10, wherein a gate oxide layer 8 has a thickness between 10 nm and 100 nm (¶39), which encompasses the claimed range of about 50 nm to about 100 nm.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to form a thickness of the gate insulating layer in the claimed range of about 50 nm to about 100 nm.
One would have been motivated to do so as Losee discloses in the trench gate power MOSFETs (fig. 4), having a thickness of the gate insulating layer between approximately 50 nm and approximately 100 nm minimizes the reverse transfer capacitance in the trench gate MOSFET (¶51 of Losee).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama in view of Nishi, as applied to claim 9 above and further in view of Joo et al. (US 20220173241 A1; hereinafter “Joo”).
In re claim 20, Koyama as modified by Nishi discloses the semiconductor device of claim 1 outlined above.
Koyama does not expressly disclose wherein the field insulating layer has a sloped surface profile extending along the length of the gate trench in the second portion.
In the same field of endeavor, Joo discloses in fig. 2, a semiconductor device, wherein a field insulating layer 215 (¶64) has a sloped surface profile extending along a length of a gate trench 210 (¶59). Joo discloses, by inclining the side wall of the trench 210 positioned closest to the end region C, the electric field concentrated on the trench edge portion may be alleviated, thereby improving a breakdown voltage (¶62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the field insulating layer of Koyama/Nishi having a sloped surface profile extending along the length of the gate trench in the second portion to reduce electric field concentrated on the trench edge portion, thereby improving a breakdown voltage (¶62 of Joo).
Claim(s) 25, 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama in view of Matsuura et al. (US 20090200607 A1; hereinafter “Matsuura”).
In re claim 25, Koyama discloses in fig. 10, a semiconductor device, comprising:
a semiconductor structure comprising an active region 40 and an inactive region 50 (¶25);
a gate bus 13 on the inactive region 50 (¶26);
a gate trench having a first portion 6 in the active region 40 and a second portion 7 in the inactive region 50 (¶26);
a gate finger 9 extending in the active region 40 in the first portion of the gate trench 6; and
a field insulating layer 10 on the inactive region 50 and in the second portion of the gate trench 7 (¶86).
Koyama does not expressly disclose wherein the gate finger extends over the field insulating layer in the second portion of the gate trench.
In the same field of endeavor, Matsuura discloses in figs. 1-3, a semiconductor device wherein a gate finger 115 (¶72-73) extends over a field insulating layer 17 (¶62) in a second portion of a gate trench 111 (¶63).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Matsuura into the device of Koyama/Nishi and alternately form the field insulating layer in the well underneath the gate interconnect. One would have been motivated to do so as Matsuura teaches the power MOSFET thus constructed offers the advantage that a sufficient current path area can be secured, since the gate interconnect lead has one of its end portions overlapping an outermost peripheral gate electrode in the cell region, for connection thereto. Thus, the power MOSFET according to the present invention allows reducing the gate resistance, and thereby shortening the switching time of the power MOSFET (¶25-26).
In re claim 41, Koyama discloses in fig. 10, a semiconductor device, comprising:
a wide bandgap semiconductor structure having an active region 40 and an inactive region 50 (¶25) (the MOSFET is a silicon carbide based MOSFET; ¶25, 35. Thus, the semiconductor structure is a wide bandgap semiconductor structure),
the active region 40 having one or more unit cell structures (the active region 40 having one MOSFET; ¶35);
a gate bus 13 (¶26);
a gate trench 6, 7 in the wide bandgap semiconductor structure 40, 50, the gate trench having a first portion 6 and a second portion 7 (¶26);
a gate finger 9 in the gate trench 6, 7 (¶26);
wherein the gate finger 9 overlaps the gate bus 13 at the second portion of the gate trench 7 (the gate finger 9 overlaps the gate bus portion 13a at the second portion of the gate trench 7); and
wherein the first portion of the gate trench 6 has a first width and the second portion of the gate trench 7 has a second width, wherein the second width is different than the first width (¶37; “The termination trench 7 is an excavation that is connected to the gate trench 6 in a plan view, with its width in the extension direction of the gate trench 6 wider than the width of the gate trench 6”).
Koyama discloses a field insulating layer 10 in the second portion of the gate trench 7 (¶86). However, Koyama does not expressly disclose the field insulating layer is between the gate finger and the wide bandgap semiconductor structure.
In the same field of endeavor, Matsuura discloses in figs. 1-3, a semiconductor device wherein a field insulating layer 17 (¶62) is between a gate finger 115 (¶72-73) and a semiconductor structure 8, 6 (¶44).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Matsuura into the device of Koyama/Nishi and alternately form the field insulating layer in the semiconductor structure underneath the gate interconnect. One would have been motivated to do so as Matsuura teaches the power MOSFET thus constructed offers the advantage that a sufficient current path area can be secured, since the gate interconnect lead has one of its end portions overlapping an outermost peripheral gate electrode in the cell region, for connection thereto. Thus, the power MOSFET according to the present invention allows reducing the gate resistance, and thereby shortening the switching time of the power MOSFET (¶25-26).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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