Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Examiner acknowledges the preliminary amendments filed on 09/27/2023.
Applicant has cancelled claims 13, 16-19, 22, 26-40, and 42-60 without prejudice or disclaimer. Claim 15 is currently amended. Claims 1-12, 14-15, 20-21, 23-25 and 41are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, 14-15, 21, 23-25, and 41 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Koyama et al. (US 20250185285 A1; hereinafter “Koyama”).
In re claim 1, Koyama discloses in fig. 10 a semiconductor device (¶25), comprising:
a semiconductor structure (40, 50) (Applicant’s definition of the semiconductor structure, “[0051] As is shown in FIG. 2B, the power semiconductor device 100 includes a semiconductor structure that includes an active region 102 and an inactive region 104”. Koyama discloses “the semiconductor device includes an active region 40, which is a region in which a main current flows when the semiconductor device is in an operating state, and a termination region 50, which is a region outside the active region 40” including a semiconductor substrate 1; fig. 1, ¶25);
a gate finger 9 in a gate trench (6, 7) in the semiconductor structure (40, 50) (fig. 1, ¶26); and
wherein the gate trench (6, 7) extends a length in the semiconductor structure (in fig. 10, gate trench 6, 7 extends a length in a direction perpendicular to a 2D surface, that is into the page),
the gate trench (6, 7) having a first portion 6 having a first width and a second portion 7 having a second width, wherein the second width is different than the first width (¶37; “The termination trench 7 is an excavation that is connected to the gate trench 6 in a plan view, with its width in the extension direction of the gate trench 6 wider than the width of the gate trench 6”).
In re claim 2, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the second width is greater than the first width (¶37).
In re claim 4, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the second portion 7 has a different shape relative to the first portion 6.
In re claim 6, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the second portion of the gate trench 7 is contiguous with an adjacent gate trench 6.
In re claim 7, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor device further comprises a gate bus 13, wherein the gate bus 13 overlaps at least a portion of the gate finger 9 in the second portion of the gate trench 7 (fig. 2; ¶26; the gate lead-out portion of the gate bus 13 overlaps the gate finger 9 in the second portion of the gate trench 7).
In re claim 8, Koyama discloses in fig. 10, the semiconductor device of claim 7, wherein the gate finger 9 and the gate bus 13 extend in different directions (e.g., in fig.1, and gate fingers in the trench 6 extend in East-West direction and a portion of the gate bus 13 extends in North-South direction).
In re claim 9, Koyama discloses in fig. 10, the semiconductor device of claim 7, further comprising a field insulating layer 10 between the gate bus 13 and the semiconductor structure 1 (¶86).
In re claim 14, Koyama discloses in fig. 10, the semiconductor device of claim 9, wherein the field insulating layer 10 is in the second portion of the gate trench 7.
In re claim 15, Koyama discloses in fig. 10, the semiconductor device of claim 14, wherein the field insulating layer 10 has a first thickness on a bottom surface of the gate trench 7 (a first thickness of the field insulating layer 10 below the top corner 7a) and a second thickness on a sidewall of the gate trench (i.e., the horizontal portion of the field insulating layer 10 underneath the second gate electrode outer periphery 13b), the first thickness being different than the second thickness.
In re claim 21, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor structure is a wide bandgap semiconductor structure (the MOSFET is a silicon carbide based MOSFET; ¶24, 30. Thus, the semiconductor structure is a wide bandgap semiconductor structure).
In re claim 23, Koyama discloses in fig. 10, the semiconductor device of claim 21, wherein the wide bandgap semiconductor structure comprises silicon carbide (¶24, 30).
In re claim 24, Koyama discloses in fig. 10, the semiconductor device of claim 1, wherein the semiconductor device is a MOSFET (¶35).
In re claim 25, Koyama discloses in fig. 10, a semiconductor device, comprising:
a semiconductor structure comprising an active region 40 and an inactive region 50 (¶25);
a gate bus 13 on the inactive region 50 (¶26);
a gate trench having a first portion 6 in the active region 40 and a second portion 7 in the inactive region 50 (¶26);
a gate finger 9 extending in the active region 40 in the first portion of the gate trench 6; and
a field insulating layer 10 on the inactive region 50 and in the second portion of the gate trench 7 (¶86).
In re claim 41, Koyama discloses in fig. 10, a semiconductor device, comprising:
a wide bandgap semiconductor structure having an active region 40 and an inactive region 50 (¶25) (the MOSFET is a silicon carbide based MOSFET; ¶25, 35. Thus, the semiconductor structure is a wide bandgap semiconductor structure),
the active region 40 having one or more unit cell structures (the active region 40 having one MOSFET; ¶35);
a gate bus 13 (¶26);
a gate trench 6, 7 in the wide bandgap semiconductor structure 40, 50, the gate trench having a first portion 6 and a second portion 7 (¶26);
a gate finger 9 in the gate trench 6, 7 (¶26);
a field insulating layer 10 in the second portion of the gate trench 7 (¶86);
wherein the gate finger 9 overlaps the gate bus 13 at the second portion of the gate trench 7 (the gate finger 9 overlaps the gate bus portion 13a at the second portion of the gate trench 7); and
wherein the first portion of the gate trench 6 has a first width and the second portion of the gate trench 7 has a second width, wherein the second width is different than the first width (¶37; “The termination trench 7 is an excavation that is connected to the gate trench 6 in a plan view, with its width in the extension direction of the gate trench 6 wider than the width of the gate trench 6”).
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Koyama et al. (US 20250185285 A1; hereinafter “Koyama”), in an alternative interpretation.
In re claim 1, Koyama discloses in figs. 1-8, a semiconductor device (¶25), comprising:
a semiconductor structure (40, 50) (Applicant’s definition of the semiconductor structure, “[0051] As is shown in FIG. 2B, the power semiconductor device 100 includes a semiconductor structure that includes an active region 102 and an inactive region 104”. Koyama discloses “the semiconductor device includes an active region 40, which is a region in which a main current flows when the semiconductor device is in an operating state, and a termination region 50, which is a region outside the active region 40” including a semiconductor substrate 1; fig. 1, ¶25);
a gate finger 9 in a gate trench (6, 7) in the semiconductor structure (40, 50) (fig. 1, ¶26); and
wherein the gate trench (6, 7) extends a length in the semiconductor structure (in fig. 2, gate trench 6, 7 extends a length in a direction perpendicular to a 2D surface, that is into the page),
the gate trench (6, 7) having a first portion 7 having a first width and a second portion 6 having a second width, wherein the second width is different than the first width (¶37; “The termination trench 7 is an excavation that is connected to the gate trench 6 in a plan view, with its width in the extension direction of the gate trench 6 wider than the width of the gate trench 6”).
In re claim 3, Koyama discloses in figs. 1-8, the semiconductor device of claim 1, wherein the second width is less than the first width (¶37).
Claim(s) 1, 7, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuura et al. (US 20090200607 A1; hereinafter “Matsuura”)
In re claim 1, Matsuura discloses in figs. 1-3, a semiconductor device 101 (¶37-38), comprising:
a semiconductor structure (semiconductor structure comprising a semiconductor substrate 6 in a cell region E and the peripheral region surrounding the cell region E have been interpreted as a semiconductor structure; ¶37);
a gate finger in a gate trench 11, 111 in the semiconductor structure (¶44); and
wherein the gate trench 11, 111 extends a length in the semiconductor structure (as shown in fig. 1B),
the gate trench having a first portion 11 having a first width (W) and a second portion 111 having a second width (W X 3) (¶49),
wherein the second width (W X 3) is different than the first width (W).
In re claim 7, Matsuura discloses in figs. 1-3, the semiconductor device of claim 1, wherein the semiconductor device further comprises a gate bus 115, wherein the gate bus 115 overlaps at least a portion of the gate finger 114 in the second portion of the gate trench 111 (¶48).
In re claim 9, Matsuura discloses in figs. 1-3, the semiconductor device of claim 7, further comprising a field insulating layer 17 between the gate bus 115 and the semiconductor structure 6 (¶62).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama as applied to claims 1 and 9 above, respectively.
In re claim 5, Koyama discloses in fig. 10, the semiconductor device of claim 1 outlined above.
Koyama discloses wherein the first portion 6 has a first length, the second portion 7 has a second length. Koyama does not expressly disclose wherein the first length is at least 10 times greater than the second length.
Koyama discloses a plurality of the strip shaped trenches 6 in the first portion and a single outer trench 7 in the second portion. Therefore, the first portion 6 has a first length which is a summation of all the strip shaped trenches 6. Koyama further discloses the strips of the gate trench 6 improve the performance of the semiconductor device (¶35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to make the first length of the first portion of the trenches 6 at least 10 times greater than the second length of the second portion of the trench 7 to improve the performance of the semiconductor device (¶35).
Moreover, it has been held to be within the general skill of a worker in the art to select a total gate length in the active region compared to the length of the gate runner in the peripheral region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a total gate length in the active region at least 10 times greater than the second length in the peripheral region in order to improve the performance of the semiconductor device.
In re claim 10, Koyama discloses in fig. 10, the semiconductor device of claim 9, wherein the field insulating layer 10 has a thickness between 0.1 μm and 5.0 μm (¶42), which encompasses the claimed range of about 0.3 microns to about to about 0.5 microns.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to form a thickness of the field insulating layer range of about 0.3 microns to about to about 0.5 microns to reducing the electric field applied to the gate dielectric film 8 provided in the vicinity of the termination trench top corner 7a and in suppressing the destruction of the gate dielectric film 8 (¶43).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura, as applied to claim 9 above and further in view of Koyama.
In re claim 10, Matsuura discloses in figs. 1-3, the semiconductor device of claim 9 outlined above. However, Matsuura does not expressly disclose wherein the field insulating layer has a thickness in a range of about 0.3 microns to about to about 0.5 microns.
In the same field of endeavor, Koyama discloses in fig. 10, a semiconductor device, wherein a field insulating layer 10 has a thickness between 0.1 μm and 5.0 μm (¶42), which encompasses the claimed range of about 0.3 microns to about to about 0.5 microns.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to form a thickness of the field insulating layer range of about 0.3 microns to about to about 0.5 microns to reducing the electric field applied to the gate dielectric film 8 provided in the vicinity of the termination trench top corner 7a and in suppressing the destruction of the gate dielectric film 8 (¶43).
In re claim 11, Matsuura, as modified by Koyama, discloses the semiconductor device of claim 10 outlined above.
Matsuura further discloses in figs. 1-3, the semiconductor device further comprising a gate oxide layer 13 between the field insulating layer 17 and the gate bus 115 (¶65).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura in view of Koyama, as applied to claim 11 above and further in view of Losee et al. (US 20150155355 A1; hereinafter “Losee”).
In re claim 12, Matsuura, as modified by Koyama, discloses the semiconductor device of claim 10 outlined above.
Matsuura does not expressly disclose wherein the gate oxide layer has a thickness of about 50 nm to about 100 nm.
Koyama discloses in fig. 10, wherein a gate oxide layer 8 has a thickness between 10 nm and 100 nm (¶39), which encompasses the claimed range of about 50 nm to about 100 nm.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Koyama to form a thickness of the gate insulating layer in the claimed range of about 50 nm to about 100 nm.
One would have been motivated to do so as Losee discloses in the trench gate power MOSFETs (fig. 4), having a thickness of the gate insulating layer between approximately 50 nm and approximately 100 nm minimizes the reverse transfer capacitance in the trench gate MOSFET (¶51 of Losee).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyama, as applied to claim 9 above and further in view of Joo et al. (US 20220173241 A1; hereinafter “Joo”).
In re claim 20, Koyama discloses the semiconductor device of claim 9 outlined above.
Koyama does not expressly disclose wherein the field insulating layer has a sloped surface profile extending along the length of the gate trench in the second portion.
In the same field of endeavor, Joo discloses in fig. 2, a semiconductor device, wherein a field insulating layer 215 (¶64) has a sloped surface profile extending along a length of a gate trench 210 (¶59). Joo discloses, by inclining the side wall of the trench 210 positioned closest to the end region C, the electric field concentrated on the trench edge portion may be alleviated, thereby improving a breakdown voltage (¶62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the field insulating layer of Koyama having a sloped surface profile extending along the length of the gate trench in the second portion to reduce electric field concentrated on the trench edge portion, thereby improving a breakdown voltage (¶62 of Joo).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893