DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder (i.e.; the alignment adjusting layer) that is coupled with functional language (i.e.; adjusting an energy-band alignment between the 2D material layer and the conductive layer) without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the alignment adjusting layer adjusting an energy-band alignment between the 2D material layer and the conductive layer” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitation “the alignment adjusting layer adjusting an energy-band alignment between the 2D material layer and the conductive layer”” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. For instance, description fails to disclose the alignment adjusting layer corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-10, 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2017/0098716 A1 hereinafter referred to as “Li”).
With respect to claim 1, Li discloses, in Figs.1-31, a semiconductor device comprising: a two-dimensional (2D) material layer (106) having a semiconductor characteristic; a conductive layer (116, 102) on a first surface of the 2D material layer (106) (see Par.[0034]-[0036] wherein the top and bottom 2D layers 106, 112 may be semiconductors with sizable energy bandgaps, such as transition metal dichalcogenide (TMD) semiconductors, for example; thin-TFET 100 includes a top gate 102, a top oxide layer 104, a top 2D layer 106, a back gate 108, a back oxide layer 110, a bottom 2D layer 112, a drain 114, a source 116, and an interlayer 118); and an alignment adjusting layer (112) on a second surface of the 2D material layer (106), the alignment adjusting layer (112) adjusting an energy-band alignment between the 2D material layer (106) and the conductive layer (102, 116), the second surface of the 2D material layer being different from the first surface of the 2D material layer (106) (see Par.[0038] wherein electron affinities are identified as χ.sub.2D,T and χ.sub.2D,B; conduction band edges are identified as E.sub.CT and E.sub.CB; and valence band edges of the top and bottom 2D layers 106, 112 are identified as E.sub.VT and E.sub.VB, respectively; thus, when the conduction band edge E.sub.CT of the top 2D layer 106 is higher than the valence band edge E.sub.VB of the bottom 2D layer 112, there are no states in the top 2D layer 106 into which the electrons of the bottom 2D layer 112 can tunnel/(band gap adjustment) (i.e.; electron tunneling occurs when electrons pass through an energy barrier (like a band gap)); it is submitted that the relative alignment of the conduction and valence bands (known as band alignment) in heterojunctions critically affects the tunneling process; ).
With respect to claim 2, Li discloses, in Figs.1-31, the semiconductor device, wherein the second surface of the 2D material layer is opposite the first surface of the 2D material layer.
With respect to claim 3, Li discloses, in Figs.1-31, the semiconductor device, wherein the alignment adjusting layer (112) overlaps the conductive layer (108) in a thickness direction of the 2D material layer (106).
With respect to claim 4, Li discloses, in Figs.1-31, the semiconductor device, wherein a thickness of the alignment adjusting layer is equal to or less than a thickness of the 2D material layer (see Par.[0033] wherein the 2D nature of such materials makes them virtually immune to the energy bandgap increase produced by the vertical quantization when conventional 3D semiconductors are thinned to a nanoscale thickness and, thus, immune to the corresponding degradation of the tunneling current density; see Par.[0035] wherein the example top and bottom 2D layers 106, 112 may be atomically-thick monolayer 2D crystals whose surfaces are free, or at least substantially free, from dangling bonds).
With respect to claim 5, Li discloses, in Figs.1-31, the semiconductor device, wherein the alignment adjusting layer includes a 2D material having an insulating property.
With respect to claim 6, Li discloses, in Figs.1-31, the semiconductor device, wherein the alignment adjusting layer includes a material capable of providing the 2D material layer with holes (see Par.[0038] wherein this scenario corresponds to an OFF state of the example Thin-TFET 100, as represented in FIGS. 4-5. In FIG. 4, though, actual numbers have been substituted in that correspond to the allowed energies of WSe.sub.2 and SnSe.sub.2, based on effective masses for holes being 0.4 m.sub.0 and for electrons being 0.3 m.sub.0 for both WSe.sub.2 and SnSe.sub.2).
With respect to claim 7, Li discloses, in Figs.1-31, the semiconductor device, wherein a work function of the alignment adjusting layer is greater than an ionization energy of the 2D material layer (see Par.[0039] wherein Equation (2) including work function is based on an assumption that majority carriers of the top and bottom 2D layers 106, 112 are at thermodynamic equilibrium with their Fermi levels, with the split of the Fermi levels set by the external voltages (i.e., E.sub.FB−E.sub.FT=eV.sub.DS), and the electrostatic potential essentially constant in the top and bottom 2D layers 106, 112; see Par.[0077] wherein the back gate 108 of the example Thin-TFET comprises p++ Silicon, which has a work function of 5.17 eV. Further, in some examples, the top and bottom oxide layers 104, 110 have an effective oxide thickness (EOT) of 1 nm. In one example, the top 2D layer 106 comprises hexagonal monolayer MoS.sub.2, while the bottom 2D layer 112 comprises hexagonal monolayer WTe.sub.2. For purposes of discussion here, and at least in some examples, an n-type and p-type doping density of 10.sup.12 cm.sup.−2 by impurities and full ionization are present in, respectively, the top and bottom 2D layers 106, 112, and the relative dielectric constant of the interlayer 118 material is 4.2 (e.g., boron nitride)).
With respect to claim 9, Li discloses, in Figs.1-31, the semiconductor device, wherein the alignment adjusting layer includes a material capable of providing the 2D material layer with electrons (see Par.[0038] wherein bottom 2D layer 112, there are no states in the top 2D layer 106 into which the electrons of the bottom 2D layer 112 can tunnel).
With respect to claim 10, Li discloses, in Figs.1-31, the semiconductor device, wherein a work function of the alignment adjusting layer is less than an electron affinity of the 2D material layer (see Par.[0038] wherein reference now to FIG. 3, a band diagram 180 corresponding to the example Thin-TFET 100 of FIG. 1 is shown. In this example, work functions are identified as Φ.sub.T and Φ.sub.B; Fermi levels of the top and back gates 102, 108 are identified as E.sub.F,MT and E.sub.F,MB, respectively; electron affinities are identified as χ.sub.2D,T and χ.sub.2D,B).
With respect to claim 12, Li discloses, in Figs.1-31, the semiconductor device, wherein the 2D material layer includes transition metal dichalcogenide (TMD) (see Par.[0032] wherein monolayers of group-VIB transition metal dichalcogenides (TMDs) according to the formula MX.sub.2—where M=Mo or W, and where X=S, Se, or Te—have recently attracted attention for their electronic and optical properties).
With respect to claim 13, Li discloses, in Figs.1-31, the semiconductor device, wherein the TMD includes a metal element and a chalcogen element, the metal element includes one of W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and the chalcogen element includes one of S, Se, and Te.
With respect to claim 14, Li discloses, in Figs.1-31, the semiconductor device, wherein a thickness of the 2D material layer is 3 nm or less (see Par.[0032] wherein monolayers of TMDs have a bandgap that varies from almost zero to 2 eV with a sub-nanometer thickness).
With respect to claim 15, Li discloses, in Figs.1-31, the semiconductor device, wherein the conductive layer (120, 116) includes a metal material.
Claims 1-7, 9-10, 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sarkar et al. (US 2023/0240088 A1 hereinafter referred to as “Sarkar”).
With respect to claim 1, Sarkar discloses, in Figs.1-14, a semiconductor device comprising: a two-dimensional (2D) material layer (40) having a semiconductor characteristic; a conductive layer (20) on a first surface/(lower surface) of the 2D material layer (40) (see Par.[0055]-[0056] wherein the transistor structure 100 may generally be formed with a bottom electrode 20, e.g. configured to operate as a gate electrode, an insulating layer 30 separating between the bottom electrode 20 and the channel region 40; the channel region 40 is formed of a layer of organic semiconductor material); and an alignment adjusting layer (45) on a second surface/(upper surface) of the 2D material layer (40), the alignment adjusting layer (45) adjusting an energy-band alignment between the 2D material layer (40) and the conductive layer (20), the second surface/(upper surface) of the 2D material layer (40) being different from the first surface/(lower surface) of the 2D material layer (40) (see Par.[0027] wherein the transistor structure may further comprise one or more alignment layers located between at least one of said source and drain electrodes and the organic semiconductor channel region, said one or more alignment layers comprising organic molecules comprising moieties having affinity to said first and second metallic materials of said at least one of said source and drain electrodes, thereby aligning work function (i.e.; including band gap function) of said first and second metallic materials with said HOMO and LUMO energy levels of said organic semiconductor channel region; see Par.[0054] wherein the interlayer 45 is formed of organic or inorganic material selected to provide fine tuning/(adjustment) to the alignment of energy levels and increase efficiency of the transistor structure 100; see Par.[0061]-[0066] wherein this organic semiconductor provides balanced n-and p-type OFET performance, enabling selecting operation by transmission of electrons and holes using electrode configuration as described above. As mentioned, the transistor performance may be further enhanced using interlayer 45 which enables tuning of the energy level alignment; as described in more detail further below, the interlayer 45 may be provided by self-generated interlayer technique; a variety of low bandgap conjugated polymers have been and are being developed for use in organic transistor structures; some of such polymers are based on alternating electron donor-acceptor (D-A) units in the polymer backbone; this structure provides electron-rich and electron-deficient moieties coupled between them and reducing the bond length alternation and the band gap).
With respect to claim 2, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the second surface/(upper surface) of the 2D material layer (40) is opposite the first surface/(lower surface) of the 2D material layer (40).
With respect to claim 3, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the alignment adjusting layer (45) overlaps the conductive layer (20) in a thickness direction of the 2D material layer (40).
With respect to claim 4, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein a thickness of the alignment adjusting layer (45) is equal to or less than a thickness of the 2D material layer (40) (see Fig.1).
With respect to claim 5, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the alignment adjusting layer (45) includes a 2D material having an insulating property.
With respect to claim 6, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the alignment adjusting layer (45) includes a material capable of providing the 2D material layer (40) with holes (see Par.[0056] wherein the channel region 40 is formed of a layer of organic semiconductor material. Differently than silicon or other inorganic semiconductors, where type of doping (n-type of p-type) determines electric conductivity to electrons or holes, organic semiconductors can conduct both electrons and holes within the same material; see Par.[0061] wherein this organic semiconductor provides balanced n- and p-type OFET performance, enabling selecting operation by transmission of electrons and holes using electrode configuration as described above; as mentioned, the transistor performance may be further enhanced using interlayer 45 which enables tuning of the energy level alignment).
With respect to claim 7, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein a work function of the alignment adjusting layer is greater than an ionization energy of the 2D material layer (see Par.[0057] wherein specifically, the first metallic material (62, 66) is selected as having work function that is substantially aligned (e.g. within up to 0.4 eV difference) with HOMO energy level of the organic semiconductor material of the channel 40, and the second metallic material (64, 68) is selected as having work function that is substantially aligned (e.g. within up to 0.4 eV difference) with LUMO energy level of the organic semiconductor material of the channel; see Par.[0060] wherein the organic semiconductor used is DPP-T-TT polymer (PDPP2T-TT-OD) having HOMO and LUMO energy levels are respectively at 5.2 eV and 3.8 eV. Accordingly, in this example the first metallic material may be selected as gold (Au) having work function of about 5.1 eV, and the second metallic material used may be Aluminum (Al) having work function of about 4.1 eV; see Par.[0077] wherein the drain current at low source-drain voltages indicates nonlinear behavior associated with non-ohmic organic-metal contact; this is a result of energy level mismatch at metal work-function and semiconductor energy level; therefore, it indicates that due to the mismatch of energy levels, aluminum and gold do not form an ohmic contact with the LUMO and HOMO level of the DPP-T-TT, respectively).
With respect to claim 9, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the alignment adjusting layer includes a material capable of providing the 2D material layer with electrons.
With respect to claim 10, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein a work function of the alignment adjusting layer is less than an electron affinity of the 2D material layer (see Par.[0057] wherein specifically, the first metallic material (62, 66) is selected as having work function that is substantially aligned (e.g. within up to 0.4 eV difference) with HOMO energy level of the organic semiconductor material of the channel 40, and the second metallic material (64, 68) is selected as having work function that is substantially aligned (e.g. within up to 0.4 eV difference) with LUMO energy level of the organic semiconductor material of the channel; see Par.[0060] wherein the organic semiconductor used is DPP-T-TT polymer (PDPP2T-TT-OD) having HOMO and LUMO energy levels are respectively at 5.2 eV and 3.8 eV. Accordingly, in this example the first metallic material may be selected as gold (Au) having work function of about 5.1 eV, and the second metallic material used may be Aluminum (Al) having work function of about 4.1 eV; see Par.[0077] wherein the drain current at low source-drain voltages indicates nonlinear behavior associated with non-ohmic organic-metal contact; this is a result of energy level mismatch at metal work-function and semiconductor energy level; therefore, it indicates that due to the mismatch of energy levels, aluminum and gold do not form an ohmic contact with the LUMO and HOMO level of the DPP-T-TT, respectively).
With respect to claim 15, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the conductive layer includes a metal material.
With respect to claim 16, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the conductive layer includes a first conductive layer (54) and a second conductive layer (52), the first conductive layer and the second conductive layer are spaced apart from each other, and the alignment adjusting layer (45) includes a first alignment adjusting layer (45) overlapping the first conductive layer (54) and a second alignment adjusting layer (45) overlapping the second conductive layer (52) in a thickness direction of the 2D material layer.
With respect to claim 17, Sarkar discloses, in Figs.1-14, the semiconductor device, further comprising a transistor, wherein the 2D material layer is a channel layer of the transistor, a first one of the first conductive layer and the second conductive layer is a source electrode of the transistor, and a second one of the first conductive layer and the second conductive layer is a drain electrode of the transistor.
With respect to claim 18, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the alignment adjusting layer is spatially spaced apart from the gate electrode of the transistor.
With respect to claim 19, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the first alignment adjusting layer and the second alignment adjusting layer are connected as different regions of a same alignment adjusting layer.
With respect to claim 20, Sarkar discloses, in Figs.1-14, the semiconductor device, wherein the transistor includes a gate insulating layer, and the first alignment adjusting layer, the second alignment adjusting layer, or both the first alignment adjusting layer and the second alignment adjusting layer contact the gate insulating layer.
Claims 1-6, 8-13, 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2022/0140100 A1 hereinafter referred to as “Cho”).
With respect to claim 1, Cho discloses, in Figs.1-11, a semiconductor device comprising: a two-dimensional (2D) material layer (130/230/330/430) having a semiconductor characteristic; a conductive layer (110/210/310/410) on a first surface/(upper surface) of the 2D material layer (130); and an alignment adjusting layer (122/222/322/422) on a second surface/(lower surface) of the 2D material layer (130), the alignment adjusting layer (122) adjusting an energy-band alignment between the 2D material layer (130) and the conductive layer (110), the second surface/(lower surface) of the 2D material layer (130) being different from the first surface/(upper surface) of the 2D material layer (130) (see Par.[0048] wherein the semiconductor device 100 according to an embodiment may include a metal layer 110, a surface-treated semiconductor layer 120 electrically contacting the metal layer 110 and having a surface 122 treated with a material having a relatively high electron affinity, and a two-dimensional (2D) material layer 130 disposed between the metal layer 110 and the semiconductor layer 120 and having a 2D crystal structure; see Par.[0055]-[0057] wherein since the surface 122 of the semiconductor layer 120 is surface-treated with an element having a high electron affinity, the conduction band level of the semiconductor layer 120 is adjusted to be lowered; thus, the Schottky energy barrier may be lowered at the interface between the semiconductor layer 120 and the metal layer 110).
With respect to claim 2, Cho discloses, in Figs.1-11, the semiconductor device, wherein the second surface/(lower surface) of the 2D material layer (130) is opposite the first surface/(upper surface) of the 2D material layer (130).
With respect to claim 3, Cho discloses, in Figs.1-11, he semiconductor device, wherein the alignment adjusting layer (122) overlaps the conductive layer (100) in a thickness direction of the 2D material layer (130).
With respect to claim 4, Cho discloses, in Figs.1-11, the semiconductor device, wherein a thickness of the alignment adjusting layer is equal to or less than a thickness of the 2D material layer (see, for example, Figs.5A-5B, Par.[0065]-[0067] wherein the 2D material layer 130 may limit and/or prevent the surface-treating element T from being diffused to another layer, for example, the metal layer 110, by pinning the surface-treating element T on the semiconductor layer 120).
With respect to claim 5, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer includes a 2D material having an insulating property.
With respect to claim 6, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer (122) includes a material capable of providing the 2D material layer with holes (see Par.[0090] wherein the active layer 540 may be disposed between the first semiconductor layer 120/122 and the second semiconductor layer 120 to generate light while electrons and holes are combined with each other, and may have a multi-quantum well (MQW) structure or a single-quantum well (SQW) structure).
With respect to claim 8, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer includes at least one of RuCl3, NbS2, MoO3, Cr2C2O2, V2CF2, Y2CO2, Hf3C2O2, Y4C3O2, VS2, Ti4C3O2, Ti3C2O2, Cr4N3O2, V3C2O2, Mn2NO2, V4C3O2, Mn4N3O2, and V2CO2 (see Par.[0048] wherein the semiconductor device 100 according to an embodiment may include a metal layer 110, a surface-treated semiconductor layer 120 electrically contacting the metal layer 110 and having a surface 122 treated with a material having a relatively high electron affinity, and a two-dimensional (2D) material layer 130 disposed between the metal layer 110 and the semiconductor layer 120 and having a 2D crystal structure; see Par.[0061] wherein the non-carbon based 2D material is a 2D material including elements other than carbon; a typical non-carbon based 2D material includes a transition metal dichalcogenide (TMD) that is a compound of a transition metal and a chalcogen element; for example, the transition metal dichalcogenide may include MoS.sub.2, WS.sub.2, TaS.sub.2, HfS.sub.2, ReS.sub.2, TiS.sub.2, NbS.sub.2, SnS.sub.2, MoSe.sub.2, WSe.sub.2, TaSe.sub.2, HfSe.sub.2, ReSe.sub.2, TiSe.sub.2, NbSe.sub.2, SnSe.sub.2, MoTe.sub.2, WTe.sub.2, TaTe.sub.2, HfTe.sub.2, ReTe.sub.2, TiTe.sub.2, NbTe.sub.2, and SnTe.sub.2; there are various non-carbon based 2D materials other than the transition metal dichalcogenide; for example, the non-carbon based 2D material may include hexagonal BN (h-BN), phosphorene, TiOx, NbOx, MnOx, VaOx, MnO.sub.3, TaO.sub.3, WO.sub.3, MoCl.sub.2, CrCl.sub.3, RuCl.sub.3, Bila, PbCl.sub.4, GeS, GaS, GeSe, GaSe, PtSe.sub.2, In.sub.2Se.sub.3, GaTe, InS, InSe, and InTe).
With respect to claim 9, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer includes a material capable of providing the 2D material layer with electrons (see Par.[0070] wherein it may also be confirmed that an element having a high electron affinity can significantly reduce a Schottky energy barrier. Therefore, according to an embodiment, the Schottky energy barrier can be significantly reduced by surface-treating the semiconductor layer 120 with an element having an electron affinity of about 4 eV or greater; see Par.[0090] wherein the active layer 540 may be disposed between the first semiconductor layer 120 and the second semiconductor layer 120 to generate light while electrons and holes are combined with each other, and may have a multi-quantum well (MQW) structure or a single-quantum well (SQW) structure).
With respect to claim 10, Cho discloses, in Figs.1-11, the semiconductor device, wherein a work function of the alignment adjusting layer is less than an electron affinity of the 2D material layer (see Par.[0070] wherein it may also be confirmed that an element having a high electron affinity can significantly reduce a Schottky energy barrier. Therefore, according to an embodiment, the Schottky energy barrier can be significantly reduced by surface-treating the semiconductor layer 120 with an element having an electron affinity of about 4 eV or greater; see Par.[0090] wherein the active layer 540 may be disposed between the first semiconductor layer 120 and the second semiconductor layer 120 to generate light while electrons and holes are combined with each other, and may have a multi-quantum well (MQW) structure or a single-quantum well (SQW) structure).
With respect to claim 11, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer includes at least one of WO3, Ca2N, Sr2N, Ba2N, Y2C, Gd2C, Tb2C, Dy2C, Ho2C, Mn2NO2H2, Mn2CO2H2, V2CO2H2, Ti4C2O2H2, Ti2CO2H2, Ti2NO2H2, Ti4N3O2H2, Y4N3F2, Hf3C2F2, and Zr3C2F2 (see Par.[0048] wherein the semiconductor device 100 according to an embodiment may include a metal layer 110, a surface-treated semiconductor layer 120 electrically contacting the metal layer 110 and having a surface 122 treated with a material having a relatively high electron affinity, and a two-dimensional (2D) material layer 130 disposed between the metal layer 110 and the semiconductor layer 120 and having a 2D crystal structure; see Par.[0061] wherein the non-carbon based 2D material is a 2D material including elements other than carbon; a typical non-carbon based 2D material includes a transition metal dichalcogenide (TMD) that is a compound of a transition metal and a chalcogen element; for example, the transition metal dichalcogenide may include MoS.sub.2, WS.sub.2, TaS.sub.2, HfS.sub.2, ReS.sub.2, TiS.sub.2, NbS.sub.2, SnS.sub.2, MoSe.sub.2, WSe.sub.2, TaSe.sub.2, HfSe.sub.2, ReSe.sub.2, TiSe.sub.2, NbSe.sub.2, SnSe.sub.2, MoTe.sub.2, WTe.sub.2, TaTe.sub.2, HfTe.sub.2, ReTe.sub.2, TiTe.sub.2, NbTe.sub.2, and SnTe.sub.2; there are various non-carbon based 2D materials other than the transition metal dichalcogenide; for example, the non-carbon based 2D material may include hexagonal BN (h-BN), phosphorene, TiOx, NbOx, MnOx, VaOx, MnO.sub.3, TaO.sub.3, WO.sub.3, MoCl.sub.2, CrCl.sub.3, RuCl.sub.3, Bila, PbCl.sub.4, GeS, GaS, GeSe, GaSe, PtSe.sub.2, In.sub.2Se.sub.3, GaTe, InS, InSe, and InTe).
With respect to claim 12, Cho discloses, in Figs.1-11, the semiconductor device, wherein the 2D material layer includes transition metal dichalcogenide (TMD) (see Par.[0048] wherein the semiconductor device 100 according to an embodiment may include a metal layer 110, a surface-treated semiconductor layer 120 electrically contacting the metal layer 110 and having a surface 122 treated with a material having a relatively high electron affinity, and a two-dimensional (2D) material layer 130 disposed between the metal layer 110 and the semiconductor layer 120 and having a 2D crystal structure; see Par.[0061] wherein the non-carbon based 2D material is a 2D material including elements other than carbon; a typical non-carbon based 2D material includes a transition metal dichalcogenide (TMD) that is a compound of a transition metal and a chalcogen element; for example, the transition metal dichalcogenide may include MoS.sub.2, WS.sub.2, TaS.sub.2, HfS.sub.2, ReS.sub.2, TiS.sub.2, NbS.sub.2, SnS.sub.2, MoSe.sub.2, WSe.sub.2, TaSe.sub.2, HfSe.sub.2, ReSe.sub.2, TiSe.sub.2, NbSe.sub.2, SnSe.sub.2, MoTe.sub.2, WTe.sub.2, TaTe.sub.2, HfTe.sub.2, ReTe.sub.2, TiTe.sub.2, NbTe.sub.2, and SnTe.sub.2; there are various non-carbon based 2D materials other than the transition metal dichalcogenide; for example, the non-carbon based 2D material may include hexagonal BN (h-BN), phosphorene, TiOx, NbOx, MnOx, VaOx, MnO.sub.3, TaO.sub.3, WO.sub.3, MoCl.sub.2, CrCl.sub.3, RuCl.sub.3, Bila, PbCl.sub.4, GeS, GaS, GeSe, GaSe, PtSe.sub.2, In.sub.2Se.sub.3, GaTe, InS, InSe, and InTe).
With respect to claim 13, Cho discloses, in Figs.1-11, the semiconductor device, wherein the TMD includes a metal element and a chalcogen element, the metal element includes one of W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and the chalcogen element includes one of S, Se, and Te (see Par.[0049] wherein the metal layer 110 may include, for example, a metal, e.g., magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or an alloy thereof).
With respect to claim 15, Cho discloses, in Figs.1-11, the semiconductor device, wherein the conductive layer includes a metal material.
With respect to claim 16, Cho discloses, in Figs.1-11, the semiconductor device, wherein the conductive layer includes a first conductive layer (210a) and a second conductive layer (210b), the first conductive layer and the second conductive layer are spaced apart from each other, and the alignment adjusting layer includes a first alignment adjusting layer overlapping the first conductive layer and a second alignment adjusting layer overlapping the second conductive layer in a thickness direction of the 2D material layer (see Par.[0073]-[0074] wherein the first and second metal layers 210a and 210b may be a source electrode and a drain electrode of a transistor, respectively).
With respect to claim 17, Cho discloses, in Figs.1-11, the semiconductor device, further comprising a transistor, wherein the 2D material layer is a channel layer of the transistor, a first one of the first conductive layer and the second conductive layer is a source electrode of the transistor, and a second one of the first conductive layer and the second conductive layer is a drain electrode of the transistor (see Par.[0073]-[0074] wherein the first and second metal layers 210a and 210b may be a source electrode and a drain electrode of a transistor, respectively).
With respect to claim 18, Cho discloses, in Figs.1-11, the semiconductor device, wherein the alignment adjusting layer is spatially spaced apart from the gate electrode of the transistor.
With respect to claim 19, Cho discloses, in Figs.1-11, the semiconductor device, wherein the first alignment adjusting layer and the second alignment adjusting layer are connected as different regions of a same alignment adjusting layer.
With respect to claim 20, Cho discloses, in Figs.1-11, the semiconductor device, wherein the transistor includes a gate insulating layer (240), and the first alignment adjusting layer, the second alignment adjusting layer, or both the first alignment adjusting layer and the second alignment adjusting layer contact the gate insulating layer (see Par.[0076] wherein the semiconductor device may further include a gate insulating film 240 disposed on the well region 220a between the source region 220b and the drain region 220c, a gate electrode 250 disposed on the gate insulating film 240, and a spacer 260 surrounding sidewalls of the gate insulating film 240 and the gate electrode 250).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818