DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/30/2025 is acknowledged.
Allowable Subject Matter
Claims 6-7 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the removing of the vertical portion of the insulating layer comprises:
forming a mask layer to cover the horizonal portion of the insulating layer and a lower part of the vertical portion of the insulating layer;
performing a first etching process to selectively remove portions of the insulating layer not covered by the mask layer;
after the performing of the first etching process, selectively remove the mask layer; and
performing a second etching process to remove the lower part of the vertical portion of the insulating layer”, as recited in claim 6.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the removing of the second portion of the insulating layer comprises:
forming a mask layer to cover the first portion of the insulating layer and a lower part of the second portion of the insulating layer;
performing a first etching process to selectively remove an upper part of the second portion of the insulating layer;
selectively remove the mask layer; and
performing a second etching process to etch back the insulating layer to remove the lower part of the second portion of the insulating layer”, as recited in claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1- 3, 5, 8-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung) in view of Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung).
Regarding Claim 1: Chung discloses a method (see Chung, Figs.11-16 as shown below and ¶ [0024]), comprising:
PNG
media_image1.png
524
874
media_image1.png
Greyscale
PNG
media_image2.png
510
865
media_image2.png
Greyscale
PNG
media_image3.png
522
873
media_image3.png
Greyscale
PNG
media_image4.png
517
872
media_image4.png
Greyscale
PNG
media_image5.png
523
862
media_image5.png
Greyscale
PNG
media_image6.png
519
871
media_image6.png
Greyscale
receiving a workpiece (202/204/206/208) (see Chung, Fig.11 as shown above) comprising:
a fin-shaped structure comprising a channel region and a source/drain region adjacent the channel region (208), wherein the fin-shaped structure comprises a first semiconductor stack (204a) over a substrate (202) and a second semiconductor stack (204b) over the first semiconductor stack (204a) (see Chung, Fig.11 as shown above), and
a gate stack (222) over the channel region (see Chung, Fig.11 as shown above);
recessing the source/drain region to form a source/drain trench (224) (see Chung, Fig.11 as shown above);
forming a first source/drain feature (228) in the source/drain trench (224) and coupled to the first semiconductor stack (204a) (see Chung, Fig.11 as shown above);
depositing a first contact etch stop layer (CESL) (230) and a first interlayer dielectric (ILD) layer (232) over the first source/drain feature (228) (see Chung, Fig.11 as shown above);
depositing an insulating layer (242) over the workpiece, the insulating layer (242) comprising a horizonal portion on the first ILD layer (232) (see Chung, Fig.12 as shown above);
forming a second source/drain feature (248) on the horizonal portion of the insulating layer (242) (see Chung, Fig.13 as shown above); and
depositing a second CESL (250) and a second ILD layer (252) over the second source/drain feature (248) (see Chung, Fig.14 as shown above).
Chung is silent upon explicitly disclosing the processing steps of wherein the insulating layer comprising a horizonal portion and a vertical portion extending along a sidewall surface of the second semiconductor stack, wherein a thickness of the horizonal portion is greater than a thickness of the vertical portion;
removing the vertical portion of the insulating layer.
Before effective filing date of the claimed invention the disclosed processing steps were known in order to provide improved current leakage control by reducing current leakage through the fins and/or substrate and to provide reduced fringing capacitance.
For support see Lung, which teaches wherein the insulating layer (97/105) comprising a horizonal portion and a vertical portion extending along a sidewall surface of the second semiconductor stack (55), wherein a thickness of the horizonal portion is greater than a thickness of the vertical portion (see Lung, Figs.11, 13, and 14 and ¶ [0051]);
removing the vertical portion of the insulating layer (97) (see Lung, Figs.11, 13, and 14 and ¶ [0051]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chung and Lung to enable the Chung insulating layer to be formed according to the teachings of Lung because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed insulating layer of Chung and art recognized suitability for providing improved current leakage control by reducing current leakage through the fins and/or substrate and providing reduced fringing capacitance has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 2: Chung as modified teaches a method as set forth in claim 1 as above. The combination of Chung and Lung further teaches wherein the depositing of the insulating layer (97/105) comprises performing a plasma-enhanced atomic layer deposition process (PEALD) (see Lung, Fig.11 and ¶ [0052]).
Regarding Claim 3: Chung as modified teaches a method as set forth in claim 1 as above. The combination of Chung and Lung further teaches wherein the insulating layer (242) comprises silicon nitride, the first CESL (230) comprises silicon nitride, and a ratio of nitrogen concentration to silicon concentration of the insulating layer (242) is different than a ratio of nitrogen concentration to silicon concentration of the first CESL (230) (note: Chung teaches a layer 242 formed from a material including silicon nitride and silicon oxynitride; hence, it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art) (note: the first nitride layer 230 and the second nitride layer 242 necessarily have different concentration due to the nature of the processing conditions) (see Chung, Fig.12 as shown above, ¶ [0039], and ¶ [0041]).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 5: Chung as modified teaches a method as set forth in claim 1 as above. The combination of Chung and Lung further teaches wherein the depositing of the insulating layer (242) over the workpiece further forms a top portion directly over the gate stack (254) (see Chung, Fig.12 as shown above), and
a thickness of the top portion is greater than the thickness of the vertical portion (see Lung, Fig.11).
Regarding Claim 8: Chung as modified teaches a method as set forth in claim 1 as above. The combination of Chung and Lung further teaches wherein the first semiconductor stack (204a) comprises a first plurality of channel layers (208) interleaved by a first plurality of sacrificial layers (206), and the second semiconductor stack (204b) comprises a second plurality of channel layers (208) interleaved by a second plurality of sacrificial layers (206) (see Chung, Fig.11 as shown above), and the method further comprises:
after the recessing of the source/drain region to form the source/drain trench (224), performing a third etching process to selectively recess the first plurality of sacrificial layers (206) and the second plurality of sacrificial layers (206) to form a first plurality of inner spacer recesses and a second plurality of inner spacer recesses (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]), respectively;
forming a first plurality of inner spacer features (226) in the first plurality of inner spacer recesses and a second plurality of inner spacer features (226) in the second plurality of inner spacer recesses (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]);
after depositing the second CESL (250) and the second ILD layer (252), selectively removing the gate stack (222) (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]);
selectively removing the first plurality of sacrificial layers (206) and the second plurality of sacrificial layers (206) (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]); and
forming a gate structure (254) over the workpiece (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]).
Regarding Claim 9: Chung as modified teaches a method as set forth in claim 8 as above. The combination of Chung and Lung further teaches wherein the fin-shaped structure further comprises a silicon germanium layer (206M) disposed between the first semiconductor stack (204a) and the second semiconductor stack (204b), and the performing of the third etching process further removes the silicon germanium layer to form a space (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]),
wherein the forming the first plurality of inner spacer features (226) and the second plurality of inner spacer features (226) further forms a dielectric layer in the space (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]).
Regarding Claim 10: Chung as modified teaches a method as set forth in claim 9 as above. The combination of Chung and Lung further teaches wherein the horizonal portion of the insulating layer (242) is in direct contact with a bottommost inner spacer feature (226) of the second plurality of inner spacer features (226) (see Chung, Figs.14-15 as shown above).
Regarding Claim 11: Chung as modified teaches a method as set forth in claim 1 as above. The combination of Chung and Lung further teaches wherein after the removing the vertical portion of the insulating layer (242) and before the forming of the second source/drain feature (248) over the horizonal portion of the insulating layer (242), performing an etching process to pre-clean the workpiece, wherein the etching process does not substantially etch the horizonal portion of the insulating layer (242) (see Chung, Figs.12-13 as shown above).
Regarding Claim 12: Chung discloses a method (see Chung, Figs.11-16 as shown above and ¶ [0024]), comprising:
depositing a contact etch stop layer (CESL) (230) and an interlayer dielectric (ILD) layer (232) over a bottom epitaxial source/drain feature (228), wherein the bottom epitaxial source/drain feature (228) is formed in a bottom portion of a source/drain trench (224) (see Chung, Fig.11 as shown above);
etching back the CESL (230) and the ILD layer (232) to expose a top portion of the source/drain trench (224) (see Chung, Fig.11 as shown above);
performing a chemical vapor deposition (CVD) to form an insulating layer (242) over the source/drain trench (see Chung, Fig.12 as shown above and ¶ [0041]);
forming a top bottom epitaxial source/drain feature (248) on the second portion of the insulating layer (242) and in the top portion of the source/drain trench (242) (see Chung, Fig.13 as shown above).
Chung is silent upon explicitly disclosing wherein performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, wherein the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench;
removing the second portion of the insulating layer.
Before effective filing date of the claimed invention the disclosed processing steps were known in order to provide improved current leakage control by reducing current leakage through the fins and/or substrate and to provide reduced fringing capacitance.
For support see Lung, which teaches wherein performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer (97/105) over the source/drain trench (86), wherein the insulating layer (97/105) comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer (underlying layer) and a second portion extending along a sidewall surface of the top portion of the source/drain trench (86) (see Lung, Figs.11, 13, and 14 and ¶ [0051]);
removing the second portion of the insulating layer (97/105) (see Lung, Figs.11, 13, and 14 and ¶ [0051]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chung and Lung to enable the Chung insulating layer to be formed according to the teachings of Lung because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed insulating layer of Chung and art recognized suitability for providing improved current leakage control by reducing current leakage through the fins and/or substrate and providing reduced fringing capacitance has been recognized to be motivation to combine. MPEP § 2144.07.
Note: forming the Chung insulating layer according to the teachings of Lung necessarily results the Chung insulating layer to comprise “a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench” as claimed in claim 12.
Regarding Claim 13: Chung as modified teaches a method as set forth in claim 12 as above. The combination of Chung and Lung further teaches wherein, during the PEALD, a bottom surface of the top portion of the source/drain trench (86) receives a first plasma dosage, and the sidewall surface of the top portion of the source/drain trench (86) receives a second plasma dosage less than the first plasma dosage (see Lung, Fig.11 and ¶ [0052]).
Regarding Claim 14: Chung as modified teaches a method as set forth in claim 12 as above. The combination of Chung and Lung further teaches wherein, film quality of the first portion of the insulating layer (97) is better than film quality of the second portion of the insulating layer (97) (see Lung, Fig.11).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 17: Chung as modified teaches a method as set forth in claim 12 as above. The combination of Chung and Lung further teaches wherein composition of the insulating layer (242) is different than composition of the CESL (230) and composition of the ILD layer (232) (see Chung, Fig.12 as shown above).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung) and Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung) as applied to claim 3 above, and further in view of Lim et al. (U.S. 2021/0066153 A1, hereinafter refer to Lim).
Regarding Claim 4: Chung as modified teaches a method as applied to claim 3 above. The combination of Chung and Lung further teaches is silent upon explicitly disclosing wherein the ratio of nitrogen concentration to silicon concentration of the insulating layer is in a range between about 1.7 and about 1.9.
Before effective filing date of the claimed invention the disclosed ratio of nitrogen concentration to silicon concentration of the insulating layer were known to be in a range between about 1.7 and about 1.9 in order to obtain a nitrogen-rich silicon nitride layer that reduce or eliminate the diffusion of humidity and/or gases.
For support see Lim, which teaches wherein the ratio of nitrogen concentration to silicon concentration of the insulating layer is in a range between about 1.7 and about 1.9 (nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at % = 40/35 (1.14) to about 75/35 (2.4)) (see Lim, ¶ [0006]- ¶ [0007]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chung, Lung, and Lim to enable the Chung insulating layer to be formed from nitrogen-rich silicon nitride layer having the recited nitrogen concentration to silicon concentration as taught by Lim in order to reduce or eliminate the diffusion of humidity and/or gases.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung).
Regarding Claim 21: Chung discloses a method (see Chung, Figs.11-16 as shown above and ¶ [0024]), comprising:
forming a fin-shaped structure over a substrate and extending lengthwise along a first direction, the fin-shaped structure comprising a channel region and a source/drain region adjacent to the channel region (see Chung, Figs.11-16 as shown above);
forming an isolation feature (232) alongside the fin-shaped structure (see Chung, Figs.11-16 as shown above);
forming a gate stack (222 or 254) over the fin-shaped structure, the gate stack (222 or 254) extending lengthwise along a second direction different from the first direction;
forming a trench (224) extending through the source/drain region (see Chung, Fig.11 as shown above);
forming a first epitaxial feature (228) in a lower portion of the trench (224), wherein the first epitaxial feature (228) overhangs the isolation feature (232) (see Chung, Fig.11 as shown above);
depositing a first nitride layer (230) over the first epitaxial feature (228) (see Chung, Fig.11 as shown above and ¶ [0039]),
depositing a second nitride layer (242) over the first nitride layer (230), wherein first nitride layer (230) and the second nitride layer (242) have different nitrogen concentrations (note: Chung teaches a layer 242 formed from a material including silicon nitride and silicon oxynitride; hence, it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art) (note: the first nitride layer 230 and the second nitride layer 242 necessarily have different concentration due to the nature of the processing conditions) (see Chung, Fig.12 as shown above and ¶ [0041]); and
forming a second epitaxial feature (248) over the first epitaxial feature (228) and the first and second nitride layers (230/242) (see Chung, Fig.13 as shown above).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 22: Chung discloses a method as set forth in claim 21 as above. Chung further teaches wherein the first epitaxial feature (228) and the second epitaxial feature (248) comprise dopants having different doping polarities (see Chung, Fig.13 as shown above, ¶ [0038], and ¶ [0042]).
Regarding Claim 23: Chung discloses a method as set forth in claim 21 as above. Chung further teaches wherein the channel region comprises a plurality of nanostructures, the first epitaxial feature (228) is disposed adjacent to bottom nanostructures of the plurality of nanostructures, the second epitaxial feature (248) is disposed adjacent to top nanostructures of the plurality of nanostructures, and the first and second nitride layers (230/242) are disposed adjacent to nanostructures between the bottom nanostructures of the plurality of nanostructures and the top nanostructures of the plurality of nanostructures (see Chung, Figs.11-16 as shown above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812