Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 12-14 and 16-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 12, Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung) teaches a method (see Chung, Figs.11-16 and ¶ [0024]), comprising:
depositing a contact etch stop layer (CESL) (230) and an interlayer dielectric (ILD) layer (232) over a bottom epitaxial source/drain feature (228), wherein the bottom epitaxial source/drain feature (228) is formed in a bottom portion of a source/drain trench (224) (see Chung, Fig.11);
etching back the CESL (230) and the ILD layer (232) to expose a top portion of the source/drain trench (224) (see Chung, Fig.11);
performing a chemical vapor deposition (CVD) to form an insulating layer (242) over the source/drain trench (see Chung, Fig.12 and ¶ [0041]);
forming a top bottom epitaxial source/drain feature (248) on the second portion of the insulating layer (242) and in the top portion of the source/drain trench (242) (see Chung, Fig.13).
Chung is silent upon explicitly disclosing wherein performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, wherein the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench;
removing the second portion of the insulating layer.
Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung) teaches wherein performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer (97/105) over the source/drain trench (86), wherein the insulating layer (97/105) comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer (underlying layer) and a second portion extending along a sidewall surface of the top portion of the source/drain trench (86) (see Lung, Figs.11, 13, and 14 and ¶ [0051]);
removing the second portion of the insulating layer (97/105) (see Lung, Figs.11, 13, and 14 and ¶ [0051]).
The prior arts of record do not anticipate and do not render obvious such limitations of Claim 12 as: " wherein the removing of the second portion of the insulating layer comprises:
forming a mask layer to cover the first portion of the insulating layer and a lower part of the second portion of the insulating layer,
performing a first etching process to selectively remove an upper part of the second portion of the insulating layer,
selectively remove the mask layer, and
performing a second etching process to etch back the insulating layer to remove the lower part of the second portion of the insulating layer; and
forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the top portion of the source/drain trench.”
Claims 13-14 and 16-17 are allowed for the same reasons as claim 12, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the removing of the vertical portion of the insulating layer comprises:
forming a mask layer to cover the horizonal portion of the insulating layer and a lower part of the vertical portion of the insulating layer;
performing a first etching process to selectively remove portions of the insulating layer not covered by the mask layer;
after the performing of the first etching process, selectively remove the mask layer; and
performing a second etching process to remove the lower part of the vertical portion of the insulating layer”, as recited in claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2021/0265348 A1, hereinafter refer to Xie) in view of Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung) and Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung).
Regarding Claim 1: Xie discloses a method (see Xie, Figs.1-9 as shown below and ¶ [0001]), comprising:
PNG
media_image1.png
503
612
media_image1.png
Greyscale
PNG
media_image2.png
448
641
media_image2.png
Greyscale
PNG
media_image3.png
452
634
media_image3.png
Greyscale
PNG
media_image4.png
390
650
media_image4.png
Greyscale
PNG
media_image5.png
396
652
media_image5.png
Greyscale
PNG
media_image6.png
452
641
media_image6.png
Greyscale
PNG
media_image7.png
450
615
media_image7.png
Greyscale
PNG
media_image8.png
440
645
media_image8.png
Greyscale
receiving a workpiece (102/106/104) (see Xie, Fig.1 as shown below) comprising:
a fin-shaped structure (102) comprising a channel region and a source/drain region adjacent the channel region, wherein the fin-shaped structure (102) comprises a first semiconductor stack over a substrate (104), a second semiconductor stack over the first semiconductor stack, and a dummy layer (112) disposed between the first semiconductor stack and the second semiconductor stack (see Xie, Fig.1 as shown above), and
a gate stack (114) over the channel region (see Xie, Fig.1 as shown above);
recessing the source/drain region to form a source/drain trench (see Xie, Fig.2 as shown above and ¶ [0042]- ¶ [0049]);
replacing the dummy layer (112) with a dielectric material layer (202), wherein the dielectric material layer (202) is vertically overlapped with the gate stack (114) (see Xie, Figs.1-2 as shown above and ¶ [0042]- ¶ [0049]):
forming a first source/drain feature (302) in the source/drain trench and coupled to the first semiconductor stack (see Xie, Fig.4 as shown above).
Xie is silent upon explicitly disclosing wherein depositing a first contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer over the first source/drain feature;
depositing an insulating layer over the workpiece, the insulating layer comprising a horizonal portion on the first ILD layer and a vertical portion extending along a sidewall surface of the second semiconductor stack,
removing the vertical portion of the insulating layer;
forming a second source/drain feature on the horizonal portion of the insulating layer; and
depositing a second CESL and a second ILD layer over the second source/drain feature.
For support see Chung, which teaches wherein depositing a first contact etch stop layer (CESL) (230) and a first interlayer dielectric (ILD) layer (232) over the first source/drain feature (228) (see Chung, Fig.11 as shown below and ¶ [0170]);
depositing an insulating layer (242) over the workpiece, the insulating layer (242) comprising a horizonal portion on the first ILD layer (232) (see Chung, Fig.12 as shown below and ¶ [0170]),
forming a second source/drain feature (248) on the horizonal portion of the insulating layer (242) (see Chung, Fig.13 as shown below and ¶ [0170]); and
depositing a second CESL (250) and a second ILD layer (252) over the second source/drain feature (248) (see Chung, Fig.14 as shown below and ¶ [0170]).
PNG
media_image9.png
524
874
media_image9.png
Greyscale
PNG
media_image10.png
510
865
media_image10.png
Greyscale
PNG
media_image11.png
522
873
media_image11.png
Greyscale
PNG
media_image12.png
517
872
media_image12.png
Greyscale
PNG
media_image13.png
523
862
media_image13.png
Greyscale
PNG
media_image14.png
519
871
media_image14.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and Chung to enable depositing a first contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer over the first source/drain feature, depositing an insulating layer over the workpiece, the insulating layer comprising a horizonal portion on the first ILD layer, forming a second source/drain feature on the horizonal portion of the insulating layer, and depositing a second CESL and a second ILD layer over the second source/drain feature as taught by Chung in order to balance output currents from the pair of stacked transistors and provide flexibility to fit different application needs on one chip and improving device performance.
The combination of Xie and Chung is silent upon explicitly disclosing wherein the insulating layer comprising a horizonal portion and a vertical portion extending along a sidewall surface of the second semiconductor stack,
removing the vertical portion of the insulating layer.
For support see Lung, which teaches wherein the insulating layer (97/105) comprising a horizonal portion and a vertical portion extending along a sidewall surface of the second semiconductor stack (55) (see Lung, Figs.11, 13, and 14 and ¶ [0051]),
removing the vertical portion of the insulating layer (97) (see Lung, Figs.11, 13, and 14 and ¶ [0051]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie, Chung, and Lung to enable the combination of Xie’s and Chung’s insulating layer to be formed according to the teachings of Lung because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed insulating layer of the combination of Xie and Chung and art recognized suitability for providing improved current leakage control by reducing current leakage through the fins and/or substrate and providing reduced fringing capacitance has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 2: Xie as modified teaches a method as set forth in claim 1 as above. The combination of Xie, Chung, and Lung further teaches wherein the depositing of the insulating layer (97/105) comprises performing a plasma-enhanced atomic layer deposition process (PEALD) (see Lung, Fig.11 and ¶ [0052]).
Regarding Claim 3: Xie as modified teaches a method as set forth in claim 1 as above. The combination of Xie, Chung, and Lung further teaches wherein the insulating layer (242) comprises silicon nitride, the first CESL (230) comprises silicon nitride, and a ratio of nitrogen concentration to silicon concentration of the insulating layer (242) is different than a ratio of nitrogen concentration to silicon concentration of the first CESL (230) (note: Chung teaches a layer 242 formed from a material including silicon nitride and silicon oxynitride; hence, it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art) (note: the first nitride layer 230 and the second nitride layer 242 necessarily have different concentration due to the nature of the processing conditions) (see Chung, Fig.12 as shown above, ¶ [0039], and ¶ [0041]).
Regarding Claim 5: Xie as modified teaches a method as set forth in claim 1 as above. The combination of Xie, Chung, and Lung further teaches wherein the depositing of the insulating layer (242) over the workpiece further forms a top portion directly over the gate stack (254) (see Chung, Fig.12 as shown above), and
a thickness of the top portion is greater than a thickness of the vertical portion (see Lung, Fig.11).
Regarding Claim 8: Xie as modified teaches a method as set forth in claim 1 as above. The combination of Xie, Chung, and Lung further teaches wherein the first semiconductor stack (204a) comprises a first plurality of channel layers (208) interleaved by a first plurality of sacrificial layers (206), and the second semiconductor stack (204b) comprises a second plurality of channel layers (208) interleaved by a second plurality of sacrificial layers (206) (see Chung, Fig.11 as shown above), and the method further comprises:
after the recessing of the source/drain region to form the source/drain trench (224), performing a third etching process to selectively recess the first plurality of sacrificial layers (206) and the second plurality of sacrificial layers (206) to form a first plurality of inner spacer recesses and a second plurality of inner spacer recesses (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]), respectively;
forming a first plurality of inner spacer features (226) in the first plurality of inner spacer recesses and a second plurality of inner spacer features (226) in the second plurality of inner spacer recesses (see Chung, Figs.6 and 7, and ¶ [0034]- ¶ [0035]);
after depositing the second CESL (250) and the second ILD layer (252), selectively removing the gate stack (222) (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]);
selectively removing the first plurality of sacrificial layers (206) and the second plurality of sacrificial layers (206) (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]); and
forming a gate structure (254) over the workpiece (see Chung, Figs.14-15 as shown above and ¶ [0045]- ¶ [0046]).
Regarding Claim 9: Xie as modified teaches a method as set forth in claim 8 as above. The combination of Xie, Chung, and Lung further teaches wherein the dummy layer (112) comprises a silicon germanium layer, and the performing of the third etching process further removes the silicon germanium layer to form a space (see Xie, Figs.1-2 as shown above and ¶ [0042]- ¶ [0049]),
wherein the dielectric material layer (202) is formed in the space, and a width of the dielectric material layer (202) is greater than a width of one of the first plurality of inner spacer features (208) (note: the width of layer 110 is 10 nm, which is equal to the width of inner spacer 208. The width of dummy layer is 15 nm, which is equal to the width of dielectric material layer 202) (see Xie, Figs.1-2 as shown above and ¶ [0042]- ¶ [0049]).
Regarding Claim 10: Xie as modified teaches a method as set forth in claim 9 as above. The combination of Xie, Chung, and Lung further teaches wherein the horizonal portion of the insulating layer (242) is in direct contact with a bottommost inner spacer feature (226) of the second plurality of inner spacer features (226) (see Chung, Figs.14-15 as shown above).
Regarding Claim 11: Xie as modified teaches a method as set forth in claim 1 as above. The combination of Xie, Chung, and Lung further teaches wherein after the removing the vertical portion of the insulating layer (242) and before the forming of the second source/drain feature (248) over the horizonal portion of the insulating layer (242), performing an etching process to pre-clean the workpiece, wherein the etching process does not substantially etch the horizonal portion of the insulating layer (242) (see Chung, Figs.12-13 as shown above).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2021/0265348 A1, hereinafter refer to Xie), Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung), and Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung) as applied to claim 3 above, and further in view of Lim et al. (U.S. 2021/0066153 A1, hereinafter refer to Lim).
Regarding Claim 4: Xie as modified teaches a method as applied to claim 3 above. The combination of Xie, Chung, and Lung further teaches is silent upon explicitly disclosing wherein the ratio of nitrogen concentration to silicon concentration of the insulating layer is in a range between about 1.7 and about 1.9.
For support see Lim, which teaches wherein the ratio of nitrogen concentration to silicon concentration of the insulating layer is in a range between about 1.7 and about 1.9 (nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at % = 40/35 (1.14) to about 75/35 (2.4)) (see Lim, ¶ [0006]- ¶ [0007]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie, Chung, Lung, and Lim to enable the combination of Xie’s and Chung’s insulating layer to be formed from nitrogen-rich silicon nitride layer having the recited nitrogen concentration to silicon concentration as taught by Lim in order to reduce or eliminate the diffusion of humidity and/or gases.
Claim(s) 24 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2021/0265348 A1, hereinafter refer to Xie), Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung), and Lung et al. (U.S. 2022/0352348 A1, hereinafter refer to Lung) as applied to claim 8 above, and further in view of Xie et al. (U.S. 2021/0320035 A1, hereinafter refer to Xie’035).
Regarding Claim24: Xie as modified teaches a method as applied to claim 8 above. The combination of Xie, Chung, and Lung is silent upon explicitly disclosing wherein the first plurality of inner spacer features and the dielectric material layer comprise a same material.
For support see Xie’035, which teaches wherein the first plurality of inner spacer (702) features and the dielectric material layer (602) comprise a same material (silicon nitride) (see Xie’035, Fig.7 as shown below, ¶ [0039], and ¶ [0041]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie, Chung, Lung, and Xie’035 to enable the same material for forming the inner spacer features and the dielectric material layer as taught by Xie’035 since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 21-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2021/0265348 A1, hereinafter refer to Xie) in view of Chung et al. (U.S. 2022/0037497 A1, hereinafter refer to Chung).
Regarding Claim 21: Xie discloses a method (see Xie, Figs.1-9 as shown above and ¶ [0001]), comprising:
forming a fin-shaped structure (102) over a substrate (104) and extending lengthwise along a first direction, the fin-shaped structure (102) comprising a channel region and a source/drain region adjacent to the channel region, wherein the channel region comprises bottom nanostructures, top nanostructures over the bottom nanostructures, and a middle nanostructure disposed therebetween (see Xie, Figs.1-2 as shown above and ¶ [0042]- ¶ [0049]);
forming a gate stack (114 or 602) over the fin-shaped structure (102), the gate stack (114 or 602) extending lengthwise along a second direction different from the first direction (see Xie, Figs.4-6 as shown above);
forming a trench extending through the source/drain region (see Xie, Figs.1-2 as shown above and ¶ [0042]- ¶ [0049]);
forming a first epitaxial feature (302) in a lower portion of the trench, wherein the first epitaxial feature (302) and coupled to the bottom nanostructures (see Xie, Fig.4 as shown above);
depositing a first nitride layer (402) over the first epitaxial feature (302) (see Xie, Fig.4 as shown above and ¶ [0059]);
depositing a second nitride layer (402) over the first nitride layer (402) (note: the integral nitride layer 402 is equivalent to the claimed separable nitride layer because mere duplication of nitride layer has no patentable significance unless a new and unexpected result is produced) (see Xie, Fig.4 as shown above and ¶ [0059]); and
forming a second epitaxial feature (502) over the first epitaxial feature (302) and the first and second nitride layers (402) and coupled to the top nanostructures (see Xie, Fig.5 as shown above),
Xie is silent upon explicitly disclosing wherein forming an isolation feature alongside the fin-shaped structure;
forming a first epitaxial feature in a lower portion of the trench, wherein the first epitaxial feature overhangs the isolation feature;
wherein the middle nanostructure is spaced apart from the first epitaxial feature, the second epitaxial feature, and the second nitride layer.
For support see Chung, which teaches wherein forming an isolation feature (214) alongside the fin-shaped structure (204) (see Chung, Figs.11-16 as shown above, ¶ [0032], and ¶ [0170]);
forming a first epitaxial feature (228) in a lower portion of the trench, wherein the first epitaxial feature (228) overhangs the isolation feature (214) (see Chung, Figs.11-16 as shown above and ¶ [0170]);
wherein the middle nanostructure is spaced apart from the first epitaxial feature (228), the second epitaxial feature (248), and the second nitride layer (230) (see Chung, Fig.16 as shown below and ¶ [0170]).
PNG
media_image15.png
603
841
media_image15.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and Chung to enable forming an isolation feature alongside the fin-shaped structure, forming a first epitaxial feature in a lower portion of the trench, wherein the first epitaxial feature overhangs the isolation feature, and the middle nanostructure is spaced apart from the first epitaxial feature, the second epitaxial feature, and the second nitride layer as taught by Chung in order to balance output currents from the pair of stacked transistors and provide flexibility to fit different application needs on one chip and improving device performance.
Regarding Claim 22: Xie as modified teaches a method as set forth in claim 9 as above. The combination of Xie and Chung further teaches wherein the first epitaxial feature (228) and the second epitaxial feature (248) comprise dopants having different doping polarities (see Chung, Fig.13 as shown above, ¶ [0038], and ¶ [0042]).
Regarding Claim 25: Xie as modified teaches a method as set forth in claim 9 as above. The combination of Xie and Chung further teaches wherein the fin-shaped structure further comprises a dielectric material layer (202) disposed on the middle nanostructure (see Xie, Figs.4-9 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812
Prosecution Insights