Prosecution Insights
Last updated: May 29, 2026
Application No. 18/476,211

DISPLAY DEVICE INCLUDING A DISPLAY SUBSTRATE AND A POLARIZATION LAYER

Non-Final OA §102§103
Filed
Sep 27, 2023
Priority
Sep 28, 2022 — RE 10-2022-0123556
Examiner
GHEYAS, SYED I
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
555 granted / 673 resolved
+14.5% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
24 currently pending
Career history
692
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
80.8%
+40.8% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 673 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on September 27, 2023 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Species I and Sub-Species B1 (claims 1-11, 19 and 20) in the reply filed on 04/30/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamada et al. (Pub. No.: US 2020/0225524 A1). Regarding Claim 1, Yamada et al. discloses a display device comprising: a display substrate comprising a display area, a peripheral area adjacent to the display area, and a pad area extending from a side of the peripheral area in a first direction (Par. 0020-0032; Figs. 1-2; display substrate comprising substrate 21, display area AA, see annotated Fig. 1 for the peripheral area and the pad area); PNG media_image1.png 640 564 media_image1.png Greyscale a polarization layer disposed on a front surface of the display substrate, and comprising a first portion covering the display area and the peripheral area adjacent to the display area, and a second portion extending from the first portion to cover at least a portion of the pad area (Par. 0020-0032; Figs. 1-2; polarization layer 23); an integrated circuit chip disposed on the front surface of the display substrate in the pad area (Par. 0026 – it is not shown explicitly but its presence stated); and a connection element comprising a first portion disposed on the front surface of the display substrate in the pad area (Par. 0020-0032; Figs. 1-2; connection element 31 (see annotated Fig. 1)). Regarding Claim 2, Yamada et al., as applied to claim 1, discloses the display device, wherein the second portion of the polarization layer comprises: a first extension portion extending from the first portion of the polarization layer in the first direction, and covering at least a portion of the pad area adjacent to the peripheral area (please see annotated Fig. 2 pasted below); and at least one second extension portion extending from the first extension portion in the first direction (please see annotated Fig. 2 pasted below). PNG media_image2.png 548 870 media_image2.png Greyscale Regarding Claim 3, Yamada et al., as applied to claim 2, discloses the display device, wherein the second extension portion is spaced apart from the integrated circuit chip and the connection element in a plan view (please see annotated Fig. 1 in light of annotated Fig. 2 pasted above). Regarding Claim 4, Yamada et al., as applied to claim 2, discloses the display device, wherein the second extension portion is positioned adjacent to a corner of the display substrate in the pad area (please see annotated Fig. 1 in light of annotated Fig. 2 pasted above). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 9-11 are rejected under 35 U.S.C. 103 as obvious over Yamada et al. (Pub. No.: US 2020/0225524 A1), as applied to claim 1, further in view of Park et al. (Pub. No. : US 2019/0350081 A1). Regarding Claim 9, Yamada et al., as applied to claim 1, does not explicitly disclose the display device, further comprising: a cover panel disposed on a back surface of the display substrate opposite to the front surface of the display substrate; and a driving chip disposed on the cover panel. Park et al. at least implicitly teachesthe display device, further comprising: a cover panel disposed on a back surface of the display substrate opposite to the front surface of the display substrate; and a driving chip disposed on the cover panel (Par. 0063-0082; Fig. 2 – cover panel 240 ; driving chip 221). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Park et al. to adapt the display device, further comprising: a cover panel disposed on a back surface of the display substrate of Yamada et al. opposite to the front surface of the display substrate; and a driving chip disposed on the cover panel of in order to make best use of the available space. Regarding Claim 10, modified Yamada et al., as applied to claim 9, discloses the display device, wherein the connection element is spaced apart from the integrated circuit chip in the first direction and comprises a second portion extending from the first portion and curved in a direction toward the back surface of the display substrate and the second portion of the connection element is electrically connected to the driving chip (claim 10 is obvious in light of rejection of claim 9 above; modified Yamada would have the driving chip 221 of Park et al. (Fig. 2) connected to the second portion of the connection element 31 of Yamada et al. (Fig. 2)). Regarding Claim 11, modified Yamada et al., as applied to claim 9, discloses the display device, wherein the second portion of the connection element is attached to the cover panel (claim 10 is obvious in light of rejection of claim 9 above; modified Yamada would have the driving chip 221 of Park et al. (Fig. 2) connected to the second portion of the connection element 31 of Yamada et al. (Fig. 2)). Allowable Subject Matter Claims 19-20 are allowed. The following is an examiner's statement of reasons for allowance: Regarding Claim 19: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a display device comprising: a display substrate comprising a display area, a peripheral area adjacent to the display area, and a pad area extending from a side of the peripheral area in a first direction; an integrated circuit chip disposed on the display substrate in the pad area; a connection element disposed on the display substrate in the pad area; and a polarization layer disposed on the display substrate, and comprising a first portion covering at least a portion of the display area and at least a portion of the peripheral area adjacent to the display area, and a second portion extending from the first portion to cover at least a portion of the pad area adjacent, wherein at least a portion of the second portion of the polarization layer is adjacent to at least a portion of the integrated circuit chip and at least a portion of the connection element in a second direction perpendicular to the first direction. The most relevant prior art reference due to Yamada et al. (Pub. No.: US 2020/0225524 A1) substantially discloses a display device comprising: a display area, a peripheral area adjacent to the display area, and a pad area extending from a side of the peripheral area in a first direction (Par. 0020-0032; Figs. 1-2; display substrate comprising substrate 21, display area AA, see annotated Fig. 1 for the peripheral area and the pad area); PNG media_image1.png 640 564 media_image1.png Greyscale an integrated circuit chip disposed on the display substrate in the pad area (Par. 0026 – it is not shown explicitly but its presence stated); a connection element disposed on the display substrate in the pad area (Par. 0020-0032; Figs. 1-2; connection element 31 (see annotated Fig. 1)); and a polarization layer disposed on the display substrate, and comprising a first portion covering at least a portion of the display area and at least a portion of the peripheral area adjacent to the display area, and a second portion extending from the first portion to cover at least a portion of the pad area adjacent (Par. 0020-0032; Figs. 1-2; polarization layer 23). This prior art, however, does not disclose a display device comprising: wherein at least a portion of the second portion of the polarization layer is adjacent to at least a portion of the integrated circuit chip and at least a portion of the connection element in a second direction perpendicular to the first direction. Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892. However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 19 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 19 is deemed patentable over the prior arts. Regarding Claim 20: this claim is allowed because of their dependency status from claim 19. Allowable Subject Matter Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (Pub. No.: US 2018/0081225 A1) – This prior art teaches a display device comprising: a display substrate (43) comprising a display area, a peripheral area adjacent to the display area, and a pad area (P) extending from a side of the peripheral area in a first direction; a polarization layer (44_3) disposed on a front surface of the display substrate, and comprising a first portion covering the display area and the peripheral area adjacent to the display area, and a second portion extending from the first portion to cover at least a portion of the pad area (P); Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 05/14/2026 /SYED I GHEYAS/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 27, 2023
Application Filed
May 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+4.3%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 673 resolved cases by this examiner. Grant probability derived from career allowance rate.

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