Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13-16 is/are rejected under 35 U.S.C. 103 as being obvious over Chiou et al. (hereinafter Chiou, US 2022/0068856) in view of Chen et al. (hereinafter Chen, US 2024/0304535).
The applied reference (Chen) has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
In regards to independent claim 13, Chiou teaches a device comprising:
a lower substrate (Chiou, 200, Fig. 9);
an upper integrated circuit die bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds (Chiou, 100, [0032], Fig. 9);
a buffer layer on the sidewall; (Chiou, 108, Fig. 9) and
an encapsulant around the buffer layer, a top surface of the encapsulant being coplanar with a top surface of the liner layer and a top surface of the upper integrated circuit die (Chiou, 110, Fig. 9).
Chiou fails to explicitly teach:
a liner layer on a sidewall of the upper integrated circuit die and a top surface of the lower substrate.
Chen teaches:
a liner layer on a sidewall of the upper integrated circuit die and a top surface of the lower substrate (Chen, Fig. 4 108).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chiou and Chen before him before the effective filing date of the claimed invention, to modify the buffer and encapsulant on a die taught by Chiou to include a liner layer on the die and substrate surface of Chen in order to obtain encapsulant that has a liner, buffer and then encapsulant layer on a die. One would have been motivated to make such a combination because the liner layer provides increase adhesion for the dielectrics to the die and substrate.
In regards to dependent claim 14, Chiou fails to explicitly teach wherein the liner layer comprises an oxide layer and a nitride layer on the oxide layer. Chen teaches wherein the liner layer comprises an oxide layer and a nitride layer on the oxide layer (Chen, [0045], [0043])
It would have been obvious to one of ordinary skill in the art, having the teachings of Chiou and Chen before him before the effective filing date of the claimed invention, to modify the buffer and encapsulant on a die taught by Chiou to include a liner layer on the die and substrate surface of Chen in order to obtain encapsulant that has a liner, buffer and then encapsulant layer on a die. One would have been motivated to make such a combination because the liner layer provides increase adhesion for the dielectrics to the die and substrate.
In regards to dependent claim 15, Chiou teaches wherein the buffer layer comprises a stress reduction compound, and the stress reduction compound comprises a polymer material and a filler (Chiou, [0034]).
In regards to independent claim 16, Chiou teaches wherein the polymer material is a thermoplastic polymer and the filler is particles of silica (Chiou, [0034]).
Reasons for Allowance
Claim 1-12 and 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose or teach an obvious combination of the following limitations when taken with the claim as a whole:
Claim 1:
an encapsulant around the buffer layer and the upper integrated circuit dies, the encapsulant comprising a molding compound, a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound.
Claim 2-12 depend upon and allowable claim; therefore, they are allowable.
Claim 17:
forming a molding compound around the stress reduction compound, the molding compound having a third coefficient of thermal expansion, the second coefficient of thermal expansion being between the first coefficient of thermal expansion and the third coefficient of thermal expansion.
Claim 18-20 depend upon and allowable claim; therefore, they are allowable.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiou et al. (US 2022/0068856) teaches a buffer layer 108 and an encapsulant 110 in which the stress reduction material of the buffer layers 108 has a similar or greater CTE than the molding material of the encapsulant. Chiou fails to teach a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound.
Hariharan et al (US 2019/0267287) teaches a die 42 that has a sidewall liner 120 surrounded by an encapsulant 68, but fails to teach a liner layer on a sidewall of the upper integrated circuit die and a top surface of the lower substrate and that the liner layer is covered by a buffer layer.
The other references cited in the PTO-892 have similar deficiencies.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST.
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812