Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-15 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 09/28/2023 ("09-28-23 IDS") and 01/30/2025 (“01-30-25 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 09-28-23 IDS and 01-30-25 IDS are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING DRIVE CIRCUIT CONFIGURED TO OUTPUT VOLTAGES APPLIED TO PLURALITY OF GATE ELECTRODES
Claim Objections
Claims 1-15 are objected to because of the following informalities:
In the independent claim 1, “of” is missing in the fourth line between “a back surface” and “the substrate.” Appropriate correction is required.
Claims 2-15 are objected to for depending from the objected independent
claim 1.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 11, 12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2005/0161768 A1 to Sugiyama et al. ("Sugiyama").
Fig. 1 of Sugiyama has been annotated and Figs. 2 and 4 of Sugiyama have been provided to support the rejection below:
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Regarding independent claim 1, Sugiyama teaches a semiconductor device (see Figs. 1 and 2 for example) comprising:
a semiconductor element including a substrate 20, 11, 12 (para [0048] - “In the IEGT, as shown in FIG. 1, a p-type base layer 12 is formed on a first surface of an n-type base layer 11 formed of a semiconductor substrate.”; para [0050] - “a p-type emitter layer 20”), a front surface electrode 18 (para [0050] - “A common emitter electrode 18”) disposed adjacent to a front surface of the substrate 20, 11, 12, a back surface electrode 21 (para [0050] - “A collector electrode 21”) disposed adjacent to a back surface of the substrate 20, 11, 12, and a plurality of gate electrodes 15, 16a, 16b (or G1, G2) (para [0049] - “The n-type source layers 17 are respectively formed adjacent to the first gate electrode 15 and the second gate electrodes 16a, 16b via the gate insulating films 14.”) disposed adjacent to the front surface of the substrate 20, 11, 12, the semiconductor element being configured so that an electrical conduction and cutoff between the front surface electrode 18 and the back surface electrode 21 is controlled by application of voltages to the plurality of gate electrodes 15, 16a, 16b (see Fig. 4);
a control circuit 36, 31, 32 (see Fig. 4) including a connection circuit 31, 32 (para [0054] - “As shown in FIG. 4, the first gate electrode (G1) 15 and the second gate electrodes (G2) 16a and 16b are respectively connected with a first gate resistor (RG1) 31 and a second gate resistor (RG2) 32.”) that connects a drive circuit 36 (para [0054] - “A controller 36 is provided with a control unit 36a for G1 and a control unit 36b for G2, which control gate voltages of the first and second gate electrodes 15, 16a, 16b, respectively.”) and the plurality of gate electrode 15, 16a, 16b, the drive circuit 36 being configured to output the voltages applied to the plurality of gate electrodes 15, 16a, 16b (para [0055] - “FIG. 5 is a timing chart showing gate voltages VG1 and VG2 of the first and second gate electrodes 15, and, 16a, 16b in operating the IEGT shown in FIG. 4.”); and
an electrical connection member 18a (para [0063] - “Emitter contacts 18a") disposed on a front surface side of the semiconductor element (see Fig. 2) and electrically connected to the front surface electrode 18, wherein
the plurality of gate electrodes 15, 16a, 16b include a first gate electrode 15 or 16a, 16b and a second gate electrode 16a, 16b or 15,
the semiconductor element has a cell region CR1, CR2 (see Fig. 1 as annotated above),
the cell region includes a first cell region CR1 or CR2 that allows a current to flow between the front surface electrode 18 and the back surface electrode 21 when the first gate electrode 15 or 16a, 16b is applied with the voltage, and a second cell region CR2 or CR1 that allows a current to flow between the front surface electrode 18 and the back surface electrode 21 when the second gate electrode 16a, 16b or 15 is applied with the voltage, and
the semiconductor element and the control circuit are configured to generate a time difference in current cutoff between the first cell region CR1 or CR2 and the second cell region CR2 or CR1 at a time of cutting off the currents flowing through the first cell region CR1 or CR2 and the second cell region CR2 or CR1 (A limitation of “configured to generate a time difference in current cutoff between the first cell region and the second cell region at a time of cutting off the current flowing through the first cell region and the second cell region” is directed to an intended use. Here, the semiconductor device of Sugiyama is reasonably capable of being used in the manner as intended, because it teaches all of the structural limitations as recited in the limitation above. Basis in fact is further provided in paragraph [0057] and [0058] which describe the operation of selectively applying control signals to the gate electrode 15 and the gate electrodes 16a, 16b at different times.).
Regarding claim 2, a limitation of “wherein the semiconductor element and the control circuit that are configured to cut off the current in the first cell region before the current in the second cell region is cut off, at the time of current cutting off the currents flowing through the first cell region and the second cell region” is directed to an intended use. Here, the semiconductor device of Sugiyama is reasonably capable of being used in the manner as intended, because it teaches all of the structural limitations as recited in the limitation above. Basis in fact is further provided in paragraph [0057] and [0058] which describe the operation of selectively applying control signals to the first gate electrode 15 and the second gate electrodes 16a, 16b at different times.).
Regarding claim 5, Sugiyama teaches
wherein the drive circuit 36 and the first gate electrode 16a, 16b that are short-circuited (para [0056] - “…Incidentally, the second gate resistor 32 may not be provided additionally.”), and
the drive circuit 36 and the second gate electrode 15 are connected to each other via a resistor 31 (RG1).
Regarding claim 6, Sugiyama teaches
wherein the drive circuit 36 and the first gate electrode 16a, 16b that are connected to each other via a first resistor 32 (para [0056] - “At this time, a condition of VG2 < Vth can be set by connection of the second gate resistor 32 with a small resistance value. Incidentally, the second gate resistor 32 may not be provided additionally.”), and
the drive circuit 36 and the second gate electrode 15 are connected to each other via a second resistor RG1 having a resistance value larger than that of the first resistor 32 (or the wire directly connecting the drive circuit 36 and the first gate electrode 16a, 16b).
Regarding claim 11, Sugiyama teaches the first gate electrode 15 that is connected to a first drive circuit 36a,
the second gate electrode 16a, 16b is connected to a second drive circuit 36b, and
the first drive circuit 36a has a driving capability higher than that of the second drive circuit 36b (A limitation of “has a driving capability higher than that of the second drive circuit” can be construed as a statement of intended use, so it does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by the prior art. Depending on when the controller for G2 is used, the controller for G1 would have a higher driving capability than the controller for G2.).
Regarding claim 12, Sugiyama teaches the drive circuit 36 that is short-circuited to the first gate electrode 15 and the second gate electrode 16a, 16b (via resistors RG1 and RG2, respectively).
A limitation of “the first cell region has a threshold voltage larger than a threshold voltage of the second cell region” is directed to an intended operation or use of the claimed semiconductor device. Since Sugiyama teaches all of the structural limitations of claim 12, the semiconductor device of Sugiyama is reasonably capable of operating or being used as intended.
Regarding claim 15, Sugiyama teaches the connection circuit 31, 32 is disposed in a region of the semiconductor element in which no cell is arranged (see Fig. 1).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 3.
Claim 4 is allowable, because it depends from the allowable claim 3.
Claim 7 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 7.
Claim 8 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 8.
Claim 9 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 9.
Claim 10 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 10.
Claim 13 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 13.
Claim 14 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2021/0296475 A1 to Iwakaji et al.
Pub. No. US 2020/0098903 A1 to Satoh
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 17 December 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status