DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (original claims 1-10 and allegedly new claims 21-30) and Species B (Figs. 15-16, 17B, 18B and 19B) in the reply filed on 1.26.2026 is acknowledged.
Non-elected claims 11-20 of Inventions II-III have been canceled and applicant adds claims 21-30; applicant alleges original claims 1-10 and new claims 21-30 belong to the same elected invention (Invention I).
Newly submitted claims 21-30 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Original claims 1-10 and new claims 21-30 are directed to related processes. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed can have a materially different design, mode of operation, function, or effect since original claims 1-10 require the step of etching to form a recess, forming a dielectric in said etched recess and using different growing conditions for epitaxial growth of two different layers which is not required by new claims 21-30; in addition, new claims 21-30 require (claim 21) an interface between a sidewall of a semiconductor region and a sidewall of a crystalline layer and (claim 28) nanostructures and inner spacers which are not required by original claims 1-10.
Recall that MPEP 806.05 states “Related inventions in the same statutory class are considered mutually exclusive, or not overlapping in scope, if a first invention would not infringe a second invention, and the second invention would not infringe the first invention” and in this case original claims 1-10 do not infringe new claims 21-30 and vice versa. That is, claims 1-10 do not anticipate claims 21-30 nor do claims 21-30 anticipate claims 1-10.
Hence, the inventions as claimed do not encompass overlapping subject (MPEP 806.05) matter and there is nothing of record to show them to be obvious variants.
Finally, restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
the inventions have acquired a separate status in the art in view of their different classification;
the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); and/or
the prior art applicable to one invention would not likely be applicable to another invention and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-30 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Finally, as a summary, claims 1-10 are elected as drawn to Invention I (original claims 1-10) and Species B (Figs. 15-16, 17B, 18B and 19B) while claims 21-30 are withdrawn as drawn to an invention independent or distinct for the elected invention.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 63/509,802, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
In this case, “etching a semiconductor region aside of a gate stack to form a recess” of claim 1 is not disclosed in 63/509,802 which discloses the broader term patterning which does not provide support for the narrower term etching. Furthermore, no specific support for “wherein the second process conditions are different from the first process conditions” of claim 1 is found in 63/509,802.
Claims 1-10 are assigned an effective filing date of 9.28.2023 until applicant shows that 63/509,802, filed 6.23.2023, provides support for the claimed subject matter.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1.9.2025 and 6.12.2025are being considered by the examiner.
Drawings
The applicant submitted original drawings on 9.28.2023 and replacement drawings on 12.11.2023, 9.12.2025 and 1.26.2026. Marked-up copies were not submitted in any filing.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Claim Objections
Claim 8 is objected to because of the following informalities: “enhance” should read –enhanced-- since that is the correct term for PECVD. Appropriate correction is required.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) or 35 U.S.C. 102(a)(2) as being anticipated by Lung et al. (US 20220352348 A1).
Regarding claim 1, Lung discloses a method comprising:
etching a semiconductor region (66) aside of a gate stack (at least 55) to form a recess (86, Figs. 9A-9B, [0044] – “The first recesses 86 may be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes, such as RIE, NBE, or the like”);
forming a dielectric layer (105) at a bottom of the recess (Fig. 14A, [0051] – “recess dielectric layer 105 may be formed at the bottom of the recesses 86”);
selectively forming a first semiconductor layer (92A) at the bottom of the recess, wherein a bottom surface of the first semiconductor layer (92A) forms an interface with a top surface of the dielectric layer (105, Fig. 15B), with the interface extending to opposing sides of the recess (Fig. 15B), and wherein the selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions ([0073]); and
epitaxially growing a second semiconductor layer (92B and/or 92C) on the first semiconductor layer (Fig. 15B), wherein the epitaxially growing the second semiconductor layer is formed using a second deposition process under second process conditions ([0073]), and wherein the second process conditions are different from the first process conditions ([0073] – “Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations” implies different processing conditions as claimed).
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 11295983 B2).
Regarding claim 1, Xie discloses a method comprising:
etching a semiconductor region (102) aside of a gate stack (130) to form a recess (304/314, Fig. 3);
forming a dielectric layer (402) at a bottom of the recess (Figs. 4 and 8);
selectively forming a first semiconductor layer (902) at the bottom of the recess, wherein a bottom surface of the first semiconductor layer (902) forms an interface with a top surface of the dielectric layer (402), with the interface extending (without reaching) to opposing sides of the recess (Figs. 9-10), and wherein the selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions (“ALD” and “the semiconductor layer 902 is undoped poly-silicon”); and
epitaxially growing a second semiconductor layer (1204) on the first semiconductor layer, wherein the epitaxially growing the second semiconductor layer is formed using a second deposition process under second process conditions (“the in-situ doped growth process can utilize gaseous or liquid precursors applied through, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE)”), and wherein the second process conditions are different from the first process conditions (Fig. 13, different processes are disclosed for forming 902 and 1204 and therefore conditions as claimed are implied).
Regarding claim 2, Xie discloses the method of claim 1, wherein the selectively forming the first semiconductor layer (902) comprises a first deposition-and-etch cycle (Figs. 9-10) comprising:
the first deposition process to deposit (Fig. 9) a sub layer (unpatterned 902) of the first semiconductor layer (patterned 902), wherein the sub layer comprises:
a top portion (uppermost) overlapping (vertically) the gate stack (130, Fig. 9);
a sidewall portion (in 304) on (indirectly and vertically on) a sidewall (created by 314) of the semiconductor region (102), with the sidewall (of the semiconductor region) being in the recess (Fig. 9); and
a bottom portion (bottommost) at the bottom of the recess (Fig. 9); and
an etch-back process (“known semiconductor fabrication operations have been used to etch the semiconductor layer 902”) to remove the top portion and the sidewall portion, with a (whole) part of the bottom portion remaining (Fig. 10).
Regarding claim 4, Xie discloses the method of claim 2, wherein the etch-back process (Fig. 10) is performed by exposing all of the top portion (of 902), the sidewall portion (of 902), and the bottom portion (of 902) to an etching chemical (“known semiconductor fabrication operations have been used to etch the semiconductor layer” implies the use of chemicals).
Regarding claim 5, Xie discloses the method of claim, wherein the second deposition process is a continuous process (it doesn’t stop until completed), and the continuous process (Figs. 11-13) is performed until the recess (304/314 which ends vertically at a level of 130) is substantially fully filled (up to said level of 130, Fig. 13).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over by Xie et al. (US 11295983 B2) in view of Tsai et al. (US 20140264348 A1).
Regarding claim 3, Xie fails to disclose the method of claim 2, wherein the selectively forming the first semiconductor layer further comprises a second deposition-and-etch cycle after the first deposition-and-etch cycle.
Tsai discloses wherein the selectively forming the first semiconductor layer (114A/116A) further comprises a second deposition-and-etch cycle (Figs. 1D, [0019])) after the first deposition-and-etch cycle (Fig. 1B, [0016].
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the cycles of Tsai in Xie and arrive at the claimed invention so as to achieve enhanced source/drain crystalline quality (Tsai, Abstract).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over by Xie et al. (US 11295983 B2) in view of Lin et al. (US 20220320307 A1).
Regarding claim 6, Xie fails to disclose the method of claim 1, wherein the first deposition process is a directional deposition process that is performed with a bias power applied.
Lin discloses
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the process of Lin to the first deposition process of Xie and arrive at the claimed invention so as to enable means to provide directional deposition (Lin, [0071]) which would allow for deposition of layers within high aspect ratio features without voids.
Regarding claim 7, Xie/Lin fails to disclose the method of claim 6, wherein the second deposition process is performed without bias power applied.
Lin discloses bias power affects directional deposition ([0071], “directional deposition (such as bottom-up deposition, or plasma deposition with higher bias power”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select a deposition without bias power in Xie/Lin and arrive and the claimed invention in view of Lin’s disclosure cited above so as to achieve a non-directional and uniform deposition, and/or, because bias power is a process condition known to affect epitaxial deposition per [0071[ of Lin and it would be within the skill set of one of ordinary skill in the art to modify bias power (including 0W) which would have yielded predictable results.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over by Xie et al. (US 11295983 B2) in view of Wang et al. (US 20200168742 A1).
Regarding claim 8, Xie fails to disclose the method of claim 1, wherein the first deposition process is performed using plasma enhance chemical vapor deposition, and the second deposition process is performed using chemical vapor deposition.
Wang discloses wherein the first deposition process (of 240) is performed using plasma enhance chemical vapor deposition (PECVD, [0034]), and the second deposition process (of 250) is performed using chemical vapor deposition (CVD, [0038], Fig. 7A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the PECVD and CVD as claimed in Xie in view of Wang and arrive at the claimed invention so as to (i) successfully form conformal epitaxial layers around recessed layers (Wang, Figs. 6A and 6B) and (ii) form epitaxial S/D layers with a known deposition suitable for that purpose (Wang, Figs. 7A and 7B) wherein PECVD and CVD are well-known and understood methods for forming epitaxial layers within the skill set of one of ordinary skill in that and their selection would have yielded predictable results in the form of epitaxial growth.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over by Xie et al. (US 11295983 B2) in view of Tu et al. (US 20210391454 A1).
Regarding claim 9, Xie fails to disclose the method of claim 1, wherein the first semiconductor layer is amorphous, and the second semiconductor layer comprises a crystalline portion.
Tu discloses wherein the first semiconductor layer (110A, “amorphous or polycrystalline layer 110A”, [0039]) is amorphous, and the second semiconductor layer (110D, “second epitaxial layer 110D is a crystalline layer”, [0039]) comprises a crystalline portion (Fig. 4C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the layers of Tu in Xie and arrive at the claimed invention so as to increase a surface area between an epitaxial source/drain and a contact structure (Tu, [0041]).
Regarding claim 10, Xie fails to disclose the method of claim 1, wherein the first semiconductor layer is formed at a first deposition temperature, and the second semiconductor layer is deposited at a second temperature higher than the first deposition temperature.
Tu discloses wherein the first semiconductor layer (110A, amorphous, [0039]) is formed at a first deposition temperature (Tamorphous), and the second semiconductor layer (110D, crystalline, [0039]) is deposited at a second temperature (Tcrystalline) higher than the first deposition temperature ([0037]- “Tamorphous<Tpolycrystalline<Tcrystalline”, Fig. 4C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the temperatures of Tu in Xie and arrive at the claimed invention so as to increase a surface area between an epitaxial source/drain and a contact structure (Tu, [0041]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818