The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of method of manufacturing in the reply filed on 02/10/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-15 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (9,608,116).Regarding claim 1, Ching et al. teach in figures 1-41 and related text a method for manufacturing a semiconductor structure, comprising:
forming first channel structures 26, second channel structures 28, and third channel structures (another 26), wherein the first channel structures, the second channel structures, and the third channel structures in a top device region are vertically separated from the first channel structures, the second channel structures, and the third channel structures in a bottom device region (see figure 2);
forming gate dielectric layers 70 (see figure 21C) surrounding the first channel structures 26, the second channel structures, and the third channel structures;
forming dipole layers (another part of element 70 (since the dipole layers are dielectric layers) over the gate dielectric layers;
forming a dummy material 42 (see figure 5) in a first space between the first channel structures and the second channel structures and in a second space between the second channel structures and the third channel structures;
removing first portions of the dummy material 42 in the first space and the second space by performing a first etching process;
implanting first dopants 58 (see figure 10) adjacent to the dummy material 42 (see figure 6) in the first space;
removing second portions of the dummy material (in area 56, see figure 9) in the first space and the second space by performing a second etching process;
removing the dipole layers in the top device region (since the dipole layers 70 are not illustrated in figures 21A and 21B).
Ching et al. do not explicitly state forming dipole layers 70 (the dipole layers are dielectric layers) over the gate dielectric layers, and do not explicitly state removing the dipole layers 70 in the top device region.
Ching et al. teach in figure 4 and related text gate dielectric layers 36 comprising silicon oxide.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form dipole layers over the gate dielectric layers and to remove the dipole layers in the top device region in Ching et al.’s device in order to improve the device characteristics and in order to simplify the processing steps of making the device by forming the gate dielectric layers of one ONO material (instead of silicon oxide) and by reducing the size of the device (by removing the dipole layers in the top device region).
Ching et al. also do not teach implanting first dopants in the dummy material 42 and completely removing the dummy material 42.
Ching et al. teach in figure 10 and related text implanting first dopants adjacent to the dummy material 42.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to implant the first dopants in the dummy material and to completely removing the dummy material, in Ching et al.’s device in order to simplify the processing steps of making the device (by not performing accurate implantation, and in order to form the device as intended by Ching et al. (by completely removing the dummy material, since said material is “dummy material”).
Regarding claim 21, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to claim 1, including removing the dipole layer exposed by the dummy material after performing the etching process (since the dipole layers 70 are not illustrated in figures 21A and 21B at the end of forming the device), treating a first portion of the gate dielectric layer covered by the dipole layer (see figures 14A-14B), forming a gate filling layer 72 (see figure 21C) over the gate dielectric layer 72, and wherein a first portion of the dummy material 42 at a first side of the first channel structures is higher (at least part thereof) than a second portion of the dummy material at a second side of the first channel structures (see figure 26).
Regarding claim 9, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to claims 1 and 21 above, including forming a first semiconductor stack over a substrate and a second semiconductor stack over the first semiconductor stack (see figure 2), wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers 26 and second semiconductor material layers 28 alternately stacked in a first direction; patterning (see figure 3) the first semiconductor stack and the second semiconductor stack to form a first fin structure, a second fin structure, and a third fin structure longitudinally oriented in a second direction and separated from each other in a third direction different from the first direction and the second direction; removing (at least partially, see figure 4) the first semiconductor material layers in the first fin structure, the second fin structure, and the third fin structure; forming first dipole layers wrapping around the second semiconductor material layers of the first fin structure, the second fin structure, and third fin structure (see above rejection); filling a first space between the second semiconductor material layers of the first fin structure and the second fin structure and a second space between the second semiconductor material layers of the second fin structure and the third fin structure with a dummy material 42; etching the dummy material so that the dummy material has a first height in the first space and a second height in the second space in the first direction (see figure 26) ; forming a first doped region in the dummy material in the first space; etching the first doped region of the dummy material in the first space and the dummy material in the second space so that the dummy material has a third height in the first space and a fourth height in the second space in the first direction, wherein a difference between the first height and the third height is different from a difference between the second height and the fourth height (see figure 26); removing the first dipole layers not covered by the dummy material; and completely removing the dummy material (see above rejection).
Regarding claim 2, Ching et al. teach in figures 1-41 and related text that a first width of the first space is different from a second width of the second space.
Regarding claim 3, Ching et al. do not teach in figures 1-41 and related text an etching rate of the dummy material in the first space is different from an etching rate of the dummy material in the second space during the second etching process.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an etching rate of the dummy material in the first space is different from an etching rate of the dummy material in the second space during the second etching process, in Ching et al.’s device in order to obtain two different heights of dummy materials.
Regarding claim 4, Ching et al. do not teach in figures 1-41 and related text implanting second dopants in the dummy material in the second space before performing the second etching process, wherein the first dopants are different from the second dopants.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to implant second dopants in the dummy material in the second space before performing the second etching process, wherein the first dopants are different from the second, in Ching et al.’s device in order to optimize and to adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 5, Ching et al. do not teach in figures 1-41 and related text the first dopants comprise Si, C, P, Ge, As, N, or a combination thereof.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first dopants comprise Si, C, P, Ge, As, N, or a combination thereof, in Ching et al.’s device in order to simplify the processing steps of making the device by using conventional materials.
Regarding claim 6, Ching et al. do not teach in figures 1-41 and related text that a top surface of the dummy material after performing the second etching process is higher than the first channel structures, the second channel structures, and the third channel structures in the bottom device region.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a top surface of the dummy material after performing the second etching process to be higher than the first channel structures, the second channel structures, and the third channel structures in the bottom device region, in Ching et al.’s device in order to provide better protection to the device during the processing steps.
Regarding claim 7, Ching et al. teach in figures 1-41 and related text annealing the dipole layers in the bottom device region to form modified gate dielectric layers in the bottom device region (since Ching et al. teach that the etch process is formed by annealing) after completely removing the dummy material; and removing the dipole layers.
Regarding claim 10, Ching et al. do not teach in figures 1-41 and related text that a width of the first space in the third direction is greater than a width of the second space in the third direction, and the difference between the first height and the third height is smaller than the difference between the second height and the fourth height, and the first doped region comprises C, Si, or a combination thereof.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the first space in the third direction is greater than a width of the second space in the third direction, and the difference between the first height and the third height is smaller than the difference between the second height and the fourth height, and the first doped region comprises C, Si, or a combination thereof, in Ching et al.’s device in order to optimize and to adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 11, Ching et al. do not teach in figures 1-41 and related text that a width of the first space in the third direction is smaller than a width of the second space in the third direction, and the difference between the first height and the third height is greater than the difference between the second height and the fourth height, and the first doped region comprises P, As, N, Si, C, or a combination thereof.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the first space in the third direction is smaller than a width of the second space in the third direction, and the difference between the first height and the third height is greater than the difference between the second height and the fourth height, and the first doped region comprises P, As, N, Si, C, or a combination thereof, in Ching et al.’s device in order to optimize and to adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 12, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space, but except forming the first doped region and the second doped region comprise different dopants.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first doped region and the second doped region comprise different dopants, in Ching et al.’s device in order to use to use the application which requires NOMS and PMOS transistors.
Regarding claim 13, Ching et al. do not teach in figures 1-41 and related text that the first doped region is partially removed and the second doped region is completely removed before removing the first dipole layers not covered by the dummy material.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first doped region partially removed and the second doped region completely removed before removing the first dipole layers not covered by the dummy material, in Ching et al.’s device in order to optimize and to adjust the conductivity of the device.
Regarding claim 14, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space, but except forming a dopant concentration of the first doped region is different from a dopant concentration in the second doped region.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a dopant concentration of the first doped region different from a dopant concentration in the second doped region, in Ching et al.’s device in order to optimize and to adjust the conductivity of the device.
Regarding claim 15, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space and forming gate dielectric layers wrapping around the second semiconductor material layers before forming the first dipole layers and removing the first dipole layers.
Ching et al. do not teach driving metal elements in the first dipole layers into the gate dielectric layers.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to drive metal elements in the first dipole layers into the gate dielectric layers, in Ching et al.’s device in order to improve the insulation of the device.
Regarding claim 22, Ching et al. teach in figures 1-41 and related text that the first doped region and the second portion of the dummy material are at least partially removed during the etching process.
Regarding claim 23, Ching et al. teach in figures 1-41 and related text that forming a second doped region in the second portion of the dummy material after the first doped region is formed.
Regarding claim 24, Ching et al. teach in figures 1-41 and related text that forming an etching rate of the first doped region is different from an etching rate of the second doped region during the etching process.
Regarding claim 25, Ching et al. teach in figures 1-41 and related text that forming the first channel structures are vertically stacked over each other, and the gate dielectric layer is formed vertically between at least two of the first channel structures.
Regarding claim 26, Ching et al. teach in figures 1-41 and related text that forming the gate filling layer is vertically sandwiched between the at least two of the first channel structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
3/8/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800