The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21, 23-26 and 29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the disclosure for the claimed limitation of” etching the dummy material to expose a top portion of the dipole layer while a bottom portion of the dipole layer is embedded in the dummy material”, as recited in claim 21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 12-15 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (9,608,116) in view of Li et al. (2024/0071926).Regarding claim 1, Ching et al. teach in figures 1-41 and related text a method for manufacturing a semiconductor structure, comprising:
forming first channel structures 26, second channel structures 28, and third channel structures (another 26), wherein the first channel structures, the second channel structures, and the third channel structures in a top device region are vertically separated from the first channel structures, the second channel structures, and the third channel structures in a bottom device region (see figures 2 and 4);
forming first source/drain structures 58 (see figure 10) attached to the first channel structures in the bottom device region;
forming second source/drain structures (another 58) attached to the first channel structures in the top device region,
forming gate dielectric layers 70 (see figure 21C) surrounding the first channel structures 26, the second channel structures, and the third channel structures;
forming dipole layers (another part of element 70, and since the dipole layers are dielectric layers) over the gate dielectric layers;
forming a dummy material 42 (see figure 5) in a first space between the first channel structures and the second channel structures and in a second space between the second channel structures and the third channel structures;
removing first portions of the dummy material 42 in the first space and the second space by performing a first etching process;
implanting first dopants 58 (see figure 10) adjacent to the dummy material 42 (see figure 6) in the first space;
removing second portions of the dummy material (in area 56, see figure 9) in the first space and the second space by performing a second etching process;
removing the dipole layers in the top device region (since the dipole layers 70 are not illustrated in figures 21A and 21B), and
removing (at least part thereof) the dummy material 42.
Ching et al. do not teach the second source/drain structures vertically overlap the first source/drain structures, and do not explicitly state forming dipole layers 70 (the dipole layers are dielectric layers) over the gate dielectric layers, and do not explicitly state removing the dipole layers 70 in the top device region.
Ching et al. teach in figure 4 and related text gate dielectric layers 36 comprising silicon oxide.
Li et al. teach in figure 5B and related text second source/drain structures 124 vertically overlap the first source/drain structures 122.
Ching et al. and Li et al. are analogous art because they are directed to FinFet devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form second source/drain structures vertically overlap the first source/drain structures, as taught by Li et al., and to form dipole layers over the gate dielectric layers and to remove the dipole layers in the top device region in Ching et al.’s device in order to reduce the size of the device (by stacking the devices), in order to improve the device characteristics and in order to simplify the processing steps of making the device by forming the gate dielectric layers of one ONO material (instead of silicon oxide) and by reducing the size of the device (by removing the dipole layers in the top device region).
Ching et al. also do not teach implanting first dopants in the dummy material 42
Ching et al. teach in figure 10 and related text implanting first dopants adjacent to the dummy material 42.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to implant the first dopants in the dummy material in Ching et al.’s device in order to minimize parasitic leakage.
Regarding claim 2, Ching et al. teach in figures 1-41 and related text that a first width of the first space is different from a second width of the second space.
Regarding claim 3, Ching et al. do not teach in figures 1-41 and related text an etching rate of the dummy material in the first space is different from an etching rate of the dummy material in the second space during the second etching process.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an etching rate of the dummy material in the first space is different from an etching rate of the dummy material in the second space during the second etching process, in Ching et al.’s device in order to obtain two different heights of dummy materials.
Regarding claim 4, Ching et al. do not teach in figures 1-41 and related text implanting second dopants in the dummy material in the second space before performing the second etching process, wherein the first dopants are different from the second dopants.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to implant second dopants in the dummy material in the second space before performing the second etching process, wherein the first dopants are different from the second, in Ching et al.’s device in order to optimize and to adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 5, Ching et al. do not teach in figures 1-41 and related text the first dopants comprise Si, C, P, Ge, As, N, or a combination thereof.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first dopants comprise Si, C, P, Ge, As, N, or a combination thereof, in Ching et al.’s device in order to simplify the processing steps of making the device by using conventional materials.
Regarding claim 6, Ching et al. do not teach in figures 1-41 and related text that a top surface of the dummy material after performing the second etching process is higher than the first channel structures, the second channel structures, and the third channel structures in the bottom device region.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a top surface of the dummy material after performing the second etching process to be higher than the first channel structures, the second channel structures, and the third channel structures in the bottom device region, in Ching et al.’s device in order to provide better protection to the device during the processing steps.
Regarding claim 7, Ching et al. teach in figures 1-41 and related text annealing the dipole layers in the bottom device region to form modified gate dielectric layers in the bottom device region (since Ching et al. teach that the etch process is formed by annealing) after completely removing the dummy material; and removing the dipole layers.
Regarding claim 9, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to claim 1 above, including
forming a first semiconductor stack over a substrate and a second semiconductor stack over the first semiconductor stack (see figure 2), wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers 26 and second semiconductor material layers 28 alternately stacked in a first direction;
patterning (see figure 3) the first semiconductor stack and the second semiconductor stack to form a first fin structure, a second fin structure, and a third fin structure longitudinally oriented in a second direction and separated from each other in a third direction different from the first direction and the second direction;
removing (at least partially, see figure 4) the first semiconductor material layers in the first fin structure, the second fin structure, and the third fin structure;
forming first dipole layers wrapping around the second semiconductor material layers of the first fin structure, the second fin structure, and third fin structure (see above rejection);
filling a first space between the second semiconductor material layers of the first fin structure and the second fin structure and a second space between the second semiconductor material layers of the second fin structure and the third fin structure with a dummy material 42;
etching the dummy material by performing a first etching process so that the dummy material has a first height in the first space and a second height in the second space in the first direction (see figure 26);
etching the first doped region of the dummy material in the first space and the dummy material in the second space after performing the implantation process so that the dummy material has a third height in the first space and a fourth height in the second space in the first direction, wherein a difference between the first height and the third height is different from a difference between the second height and the fourth height (see figure 26);
removing the first dipole layers not covered by the dummy material; and removing the dummy material (see above rejection).
Ching et al. do not teach performing an implantation process to a first doped region in the dummy material in the first space after performing the first etching process.
Ching et al. teach in figure 10 and related text performing an implantation process to a first doped region in the dummy material in the first space after performing the first etching process.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to perform an implantation process to a first doped region in the dummy material in the first space after performing the first etching process;
in Ching et al.’s device in order to minimize parasitic leakage.
Regarding claim 12, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space, but except forming the first doped region and the second doped region comprise different dopants.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first doped region and the second doped region comprise different dopants, in Ching et al.’s device in order to use to use the application which requires NOMS and PMOS transistors.
Regarding claim 13, Ching et al. do not teach in figures 1-41 and related text that the first doped region is partially removed and the second doped region is completely removed before removing the first dipole layers not covered by the dummy material.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first doped region partially removed and the second doped region completely removed before removing the first dipole layers not covered by the dummy material, in Ching et al.’s device in order to optimize and to adjust the conductivity of the device.
Regarding claim 14, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space, but except forming a dopant concentration of the first doped region is different from a dopant concentration in the second doped region.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a dopant concentration of the first doped region different from a dopant concentration in the second doped region, in Ching et al.’s device in order to optimize and to adjust the conductivity of the device.
Regarding claim 15, Ching et al. teach in figures 1-41 and related text substantially the entire claimed structure, as applied to the claims above, including forming a second doped region in the dummy material in the second space and forming gate dielectric layers wrapping around the second semiconductor material layers before forming the first dipole layers and removing the first dipole layers.
Ching et al. do not teach driving metal elements in the first dipole layers into the gate dielectric layers.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to drive metal elements in the first dipole layers into the gate dielectric layers, in Ching et al.’s device in order to improve the insulation of the device.
Regarding claim 28, in the combined device, Ching et al. teach in figures 1-41 and related text forming a first gate filling layer wrapping 72 (see figure 16C) around a bottommost one of the second semiconductor material layers of the first fin structure; forming an isolation structure 142 (see Li et al.) over the first gate filling layer; and forming a second gate filling layer (another 72 in Li et al.’s device) wrapping around a topmost one of the second semiconductor material layers of the first fin structure, wherein the first gate filling layer is vertically spaced apart from the second gate filling layer in a cross-sectional view.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (9,608,116) and Li et al. (2024/0071926), as applied to claim 1 above, and further in view of Wu et al. (2020/0273755).Regarding claim 27, Ching et al. and Li et al. teach substantially the entire claimed structure, as applied to claim 1 above, except forming the dummy material (STI) after forming the second source/drain structures.
Wu et al. teach in figure 1 and related text (see paragraph [0073]) forming the dummy material 108 after forming the second source/drain structures 106.
Wu et al, Ching et al. and Li et al. are analogous art because they are directed to FinFet devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the dummy material (STI) after forming the second source/drain structures, as taught by Wu et al., in prior art’s device in order to provide better electrical isolation to the device.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
6/24/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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