DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 3/5/2026.
Claims 1-16 and 21-24 are pending. Claims 17-20 are cancelled. Claims 21-24 are new. Claims 1, 10 and 21 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 3/5/2026 is acknowledged.
Claims 17-20, which have been canceled, were drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/5/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claim 10 must be shown or the feature(s) canceled from the claim(s). For example, claim 10 recites the limitations “removing a remaining portion of the dummy gate structure and the second semiconductor layers to form a gate trench” and “forming a gate structure in the gate trench, wherein the gate structure comprises a gate dielectric layer wrapped around the second semiconductor layers and a gate electrode layer wrapped around the gate dielectric layer” (emphasis added), which do not appear to be shown by the Drawings of the current application for the reasons that follow. As shown in Figures 15A-15B and 24A-24B of the Drawings it appears that the semiconductor layers 106 that is removed in the first cited limitation is fully removed such that it would no longer exist in the subsequent step (as detailed in in the second cited limitation) and thereby would not be wrapped by the gate dielectric layer. The Drawings of the current application support the removal of semiconductor layers 106 that are different than the semiconductor layers 108 which are wrapped by the gate dielectric layer. That is, the same semiconductor layers are not both removed and then wrapped by the gate dielectric layer. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 recites the limitations “removing a remaining portion of the dummy gate structure and the second semiconductor layers to form a gate trench” and “forming a gate structure in the gate trench, wherein the gate structure comprises a gate dielectric layer wrapped around the second semiconductor layers and a gate electrode layer wrapped around the gate dielectric layer” (emphasis added), which do not appear to be supported by the originally filed Specification of the current application for the reasons that follow. As detailed in paragraphs [0054]-[0055] and [0085] of the Specification and Figures 15A-15B and 24A-24B of the Drawings it appears that the semiconductor layers 106 that is removed in the first cited limitation is fully removed such that it would no longer exist in the subsequent step (as detailed in in the second cited limitation) and thereby would not be wrapped by the gate dielectric layer. The Specification and Drawings of the current application support the removal of semiconductor layers 106 that are different than the semiconductor layers 108 which are wrapped by the gate dielectric layer. That is, the same semiconductor layers are not both removed and then wrapped by the gate dielectric layer.
For the purposes of prosecution, the limitation “removing a remaining portion of the dummy gate structure and the second semiconductor layers to form a gate trench” will be interpreted as “removing a remaining portion of the dummy gate structure and the first semiconductor layers to form a gate trench”, which is the configuration currently supported by the originally filed Specification. This interpretation will extend to the dependent claims of claim 10, including claim 11 which makes reference to this process.
Note the dependent claims 11-16 do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6, 16 and 23-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the terms “about” in line 2 of the claim, which is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 1 nm” without clear upper and lower limits defined for the term “about”.
Claim 6 recites the terms “about” in line 3 of the claim, which is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 2 nm” without clear upper and lower limits defined for the term “about”.
Claim 16 recites the limitation “the insulating material layer” in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 23 recites the limitation “the X-direction” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note the dependent claims 24 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (US 2022/0037491 A1, hereinafter “You”).
Regarding independent claim 10, You discloses a method of forming a semiconductor structure, comprising:
forming a dummy gate structure 120A1(“dummy gate stacks”- ¶0036) extending in a Y-direction and over a fin structure 106A1 (“fin structures”- ¶0027), wherein the fin structure 106A1 comprises first semiconductor layers 102a-102d (“semiconductor layers”- ¶0023) and second semiconductor layers 104a-104d (“semiconductor layers”- ¶0023) alternately stacked in a Z-direction (see Fig. 3A);
forming gate spacers 126’ (“gate spacers”- ¶0043) on sidewalls of the dummy gate structure 120A1 (see Fig. 3C);
removing a portion of the dummy gate structure 120A1 to form a first trench 142 (“trenches”- ¶0068, as shown in Fig. 3J) that exposes upper portions (i.e., the top halves of 126’) of the gate spacers 126’ (see Fig. 3J);
partially etching the upper portions of the gate spacers 126’ (¶0075), which leaves portions of the top halves of 126’ such that it is considered that the upper portions of 126’ are partially etched (see Fig. 3L);
forming insulating layers 150 (“gate dielectric layer”- ¶0086) on sidewalls of the etched upper portions of the gate spacers 126’ (see Fig. 3M);
removing a remaining portion 116 (“gate dielectric layer”, which is part of 120A1- ¶0039) of the dummy gate structure 120A1 and the first semiconductor layers 102a-102d to form a gate trench 142 (“trenches”- ¶0068, as shown in Fig. 3K) (¶0069) (see Fig. 3K); and
forming a gate structure in the gate trench 142, wherein the gate structure comprises a gate dielectric layer (i.e., “interfacial layers… silicon oxide”- ¶0079) wrapped around the second semiconductor layers 104a-104d and a gate electrode layer 152 (“work function layer”- ¶0077) wrapped around the gate dielectric layer (¶¶0076-0079) (see Fig. 3M).
Allowable Subject Matter
Claims 1-4, 7-9 and 21-22 are allowed.
Regarding independent claim 1, You discloses a method of forming a semiconductor structure, comprising:
forming a fin structure 106A1 (“fin structures”- ¶0027) over a substrate 100 (“substrate”- ¶0016) in a Z-direction, wherein the fin structure 106A1 comprises first semiconductor layers 102a-102d (“semiconductor layers”- ¶0023) and second semiconductor layers 104a-104d (“semiconductor layers”- ¶0023) alternately stacked (see Fig. 2B);
forming a dummy gate structure 120A1 (“dummy gate stacks”- ¶0036) extending in a Y-direction and over the fin structure (see Fig. 3A);
forming gate spacers 126’ (“gate spacers”- ¶0043) on sidewalls of the dummy gate structure 120A1 (see Fig. 3C);
removing a portion of the dummy gate structure 120A1 to form a first trench 142 (“trenches”- ¶0068, as shown in Fig. 3J) that exposes upper portions (i.e., the top halves of 126’) of the gate spacers 126’ (see Fig. 3J);
forming an insulating material 150 (“gate dielectric layer”- ¶0086) in the first trench 142 (see Fig. 3M);
partially removing the insulating material 150 to form insulating layers 150 on sidewalls of the upper portions of the gate spacers 126’ (see Fig. 3N); and
removing a remaining portion 116 (“gate dielectric layer”, which is part of 120A1- ¶0039) of the dummy gate structure 120A1 to expose lower portions of the gate spacers 126’ (see Fig. 3K).
You does not expressly disclose partially etching the lower portions of the gate spacers.
Thus, regarding independent claim 1, the claim is allowed, because the prior art of record including You, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “partially etching the lower portions of the gate spacer”.
Claims 2-4 and 7-9 are allowed as being dependent on allowed claim 1.
Regarding independent claim 21, You discloses a method of forming a semiconductor structure, comprising:
forming a fin structure 106A1 (“fin structures”- ¶0027) over a substrate 100 (“substrate”- ¶0016) in a Z-direction, wherein the fin structure 106A1 comprises first semiconductor layers 102a-102d (“semiconductor layers”- ¶0023) and second semiconductor layers 104a-104d (“semiconductor layers”- ¶0023) alternately stacked (see Fig. 2B);
forming a dummy gate structure 120A1 (“dummy gate stacks”- ¶0036) extending in a Y-direction and over the fin structure 106A1, wherein the dummy gate structure 120A1 comprises a dummy gate dielectric layer 116 (“gate dielectric layer”- ¶0039), and a dummy gate electrode layer 118 (“dummy gate electrode”- ¶0039) over the dummy gate dielectric layer 116 (see Fig. 3A);
forming gate spacers 126’ (“gate spacers”- ¶0043) on sidewalls of the dummy gate structure 120A1 (see Fig. 3C);
removing a portion of the dummy gate electrode layer 118 to expose upper portions (i.e., the top halves of 126’) of the gate spacers 126’ (see Fig. 3J);
forming insulating layers 150 (“gate dielectric layer”- ¶0086) on sidewalls of the upper portions of the gate spacers 126’ (see Fig. 3M); and
removing the dummy gate dielectric layer 116 to expose lower portions of the gate spacers 126’ (see Fig. 3K).
You does not expressly disclose removing a remaining portion of the dummy gate electrode layer and partially etching the lower portions of the gate spacers.
Regarding independent claim 21, the claim is allowed, because the prior art of record including You, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “removing a remaining portion of the dummy gate electrode layer” and “partially etching the lower portions of the gate spacers”.
Claims 22-24 are allowed as being dependent on allowed claim 21.
Claims 5-6 and 23-24 (which depend from allowed claims 1 and 21, respectively) would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liu et al. (US 2013/0049142 A1), which discloses a method of forming a semiconductor structure comprising forming gate spacers with varying widths.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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