+DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 16-20 in the reply filed on 03/12/2026 is acknowledged. Non-elected claims 1-15 have been canceled, new claims 21-35 have been added. Claims 16-35 are examined on the merits in this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 27 and 30-35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 27, the application fails to disclose the limitations “to form a remaining dummy gate structure” and “wherein the gate structure is formed on the remaining dummy gate structure”. The disclosed remaining dummy gate structure is the gate spacers [126] (Fig. 2G-4), but now dummy gate spacers are claimed separately as gate spacers. Therefore, there is no remaining dummy gate structure.
Regarding claims 30 and 31, the claims recite “a width of the middle portion is smaller than a width of the bottom portion”. The instant disclosure is silent about this limitation. The application only mentions height. Therefore, it is believed to be “new matter”. A mere scale shown in the drawings is insufficient for full disclosure of the limitation.
Claims 32-35 are rejected because they are dependent claims and contain all limitations of the independent claim 35.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 20, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leobandung., U.S. Pat. 10,586,853, hereafter Leobandung.
Regarding claim 16, Leobandung discloses (Figs 1-20) a method for forming a semiconductor structure, comprising:
forming (Fig. 3A) a stack layer [130] on a substrate [110], wherein the stack layer comprises a plurality of first (SiGe) semiconductor material layers [122],[124] and a plurality of second (Si) semiconductor material layers [123],[125] alternately stacked (Col. 8, lines 33-59);
forming (Fig. 11A) an isolation structure [142],[140] over the substrate [110], wherein the stack layer [122],[123],[124],[125] extends above the isolation structure [142],[140];
forming a dummy gate structure [DG2] over the first semiconductor material layers [122], [124], and the second semiconductor material layers [123],[125] ;
performing an etching process (Col.13, line 42 - Col. 14, line 2, Figs 12A-C) on the isolation structure [142], [140], wherein the isolation structure after the etching process comprises a first portion (thicker portion of [140] and [142] directly below [DG2], see Fig.11B) directly below the dummy gate structure [DG2] and a second portion (recessed by depth D1 portion shown in Figs 12A-12C) outside the dummy gate structure [DG2], and a top surface of the second portion is lower (by depth D1) than a top surface of the first portion; and
removing (Fig. 12A) a portion of the first semiconductor material layers [122],[124] and a first portion of second semiconductor material layers [123], [125] to form an S/D recess (a recess in isolation structure [142], [140] and between dummy gates [DG2], [DG1]), wherein a portion of the isolation structure [142], [140] is removed to form an isolation recess when forming the S/D recess (Col.13, line 42 - Col. 14, line 2, Figs 12A-C ) .
Regarding claim 20, Leobandung further discloses (Figs 16A-16C, Col. 16, lines 6-52) further comprising:
removing a portion [156], [154] of the dummy gate structure [DG2]to form a remaining dummy gate structure;
removing a second portion of the second semiconductor material layers [144], [124] to form a gap; and
forming (Fig. 17A,B) a gate structure [180], [186] in the gap, wherein the gate structure is formed on the remaining dummy gate structure [158].
Regarding claim 25, Leobandung discloses (Figs 1-20) a method for forming a semiconductor structure, comprising:
forming (Fig. 3A) a stack structure [130] on a substrate [110], wherein the stack structure comprises a plurality of first (SiGe) semiconductor material layers [122],[124] and a plurality of second (Si) semiconductor material layers [123],[125] alternately stacked (Col. 8, lines 33-59);
forming (Fig. 11A) an isolation structure [142],[140] over the substrate [110], wherein the stack structure [122],[123],[124],[125] extends above the isolation structure [142],[140];
forming a dummy gate structure [152], [154], [156] over the stack structure [122]-[125];
forming a gate spacer [158] adjacent to the dummy gate structure [152]-[156]e;
performing an etching process (Col. 11, lines 29-55, Col.13, line 42 - Col. 14, line 2, Figs 6A-C, 7A,B, 12A-C) on a portion of the isolation structure (by depth D1) [142], [140], a portion of the gate spacer layer [158] and a portion of the stack structure[122]-[125] to a recessed isolation structure [140], [142] and an S/D recess, wherein the recessed isolation structure (indicated by [D1]) is below a bottom surface of the gate spacer layer [158].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung., U.S. Pat. 10,586,853, hereafter Leobandung, in view of Ching et. al., U.S. Pat. 10,211,307, hereafter Ching
Regarding claim 17, Leobandung discloses everything as applied above. Leobandung further discloses (Fig. 20A) forming an S/D structure (e. g., [190] and [170] or [192] and [172]) in the S/D recess
Leobandung fails to explicitly disclose further comprising:
forming a fin spacer layer adjacent to the stack layer; and
wherein the S/D structure is formed adjacent to the fin spacer layer, and a bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.
However Ching discloses (Fig. 7)
forming a fin spacer layer [35] adjacent to the stack layer [20],[25]; and
wherein (Fig. 10A) the S/D structure [80] is formed adjacent to the fin spacer layer [35], and a bottom surface of the fin spacer layer [35] is lower than a bottom surface of the S/D structure [80].
It would have been obvious to one of ordinary skill in the art to modify the device structure of Leobandung with the teachings of insulating fin spacer layer of Chin, because such a layer protects sensitive fin from gases during subsequent manufacturing.
Regarding claim 18, Leobandung in view of Ching discloses everything as applied above.
Leobandung further discloses further comprising:
further comprising:
forming (Fig. 12A) a bottom isolation layer [140], [142] in the S/D recess before forming the S/D structure (Figs 14-20)
Leobandung fails to explicitly disclose
wherein the bottom isolation layer has a curved top surface.
However, Ching discloses (Figs 1B, 6)
wherein the bottom isolation layer [40] has a curved top surface.
It would have been obvious to one of ordinary skill in the art for STI to have ca curved surface, as shown in Ching, because sharp edges in STI are known to cause high concentration of electric fields and leakage current, and rounded surfaces helps to reduce leakage current.
Regarding claim 22, Leobandung discloses everything as applied above. Leobandung further discloses (Figs 15, 16, Col. 16, lines 6-52) further comprising:
Removing a second portion (inside the dummy gate [DG2], now [G2]) of second semiconductor material layers [122], [124] above a base structure [110].
Leobandung fails to explicitly disclose
wherein a top surface of the base structure is higher than a top surface of the isolation structure
However, Ching discloses (Fig. 6)
wherein a top surface of the base structure [10] is higher than a top surface of the isolation structure [40].
It would have been obvious to one of ordinary skill in the art to modify the flat base of Leobandung with the teachings of a GAA nanostructure on top of a fin in isolation structure to optimize leakage protection.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Leobandung., U.S. Pat. 10,586,853, hereafter Leobandung, in view of Chang et. al., U.S. Pat. Pub. 2021/0391477, hereafter Chang.
Regarding claim 19, Leobandung discloses everything as applied above. Leobandun further discloses further comprising (Figs 6A-6C): forming a gate spacer layer [158] adjacent to the dummy gate structure [156],[154],[152]. Leobandung fails to explicitly disclose:
wherein a bottom surface of the gate spacer layer is lower a bottom surface of the dummy gate structure.
However, Chang discloses (Fig. 9B)
forming a gate spacer layer [84] adjacent to the dummy gate structure [80],[78],[76],
wherein a bottom surface of the gate spacer layer [84] is lower a bottom surface of the dummy gate structure [80], [78], [76].
It would have been obvious to one of ordinary skill in the art to replace dummy gate spacer structure of Leobandung with the spacer layer of Chang, because Chang teaches (par. [0009]) that such a structural change allows for the nanostructures serving as channel regions to be closer to one another without unwanted interference.
Claim 23-24 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung, U.S. Pat. 10,586,853, hereafter Leobandung, in view of KR 20040008798, hereafter ‘98.
Regarding claim 23, Leobandung discloses everything as applied above.
Leobandung further discloses (Fig. 20A) further compriing:
forming an S/D structure [170], [172] in the S/D recess
Leobandung fails to explicitly disclose
further comprising:
performing a clean process on the isolation structure, such that the second portion of the isolation structure is recessed; and
forming the S/D structure in the S/D recess after the clean process.
However, ‘98 discloses (claim 2, p.8)
performing a clean process on the isolation structure, such that the second portion of the isolation structure is recessed.
It would have been obvious to one or ordinary skill in the art prior to effective date of the instant application to modify Leobandung with the clean process of ‘98, because ‘98 teaches (abstract) that rounded isolation prevents degradation due to a high electric field around sharp corners.
Regarding claim 24, Leobandung in view of ‘98 discloses everything as applied above. Leobandung further discloses further comprising:
forming an s/d contact structure[190], [192] over the s/d structure [170],[172].
Regarding claim 28, Leobandung discloses everything as applied above. Leobandung further discloses (Figs 12A-C) forming a bottom isolation layer [140],[142] in the s/d recess Leobandung fails to explicitly disclose wherein the bottom isolation layer has a curved top surface.
However, ‘98 discloses (claim 2, p.8) wherein the bottom isolation layer has a curved top surface.
It would have been obvious to one or ordinary skill in the art prior to effective date of the instant application to modify Leobandung with the clean process of ‘98, because ‘98 teaches (abstract) that rounded isolation prevents degradation due to a high electric field around sharp corners.
Regarding claim 29, Leobandung discloses everything as applied above.
Leobandung further discloses (Fig. 20A) further compriing:
forming an S/D structure [170], [172] in the S/D recess
Leobandung fails to explicitly disclose
further comprising:
performing a clean process on the isolation structure, such that the second portion of the isolation structure is recessed; and
forming the S/D structure in the S/D recess after the clean process.
However, ‘98 discloses (claim 2, p.8)
performing a clean process on the isolation structure, such that the second portion of the isolation structure is recessed.
It would have been obvious to one or ordinary skill in the art prior to effective date of the instant application to modify Leobandung with the clean process of ‘98, because ‘98 teaches (abstract) that rounded isolation prevents degradation due to a high electric field around sharp corners.
Claims 21 and 26 are rejected under 35 U.S.C. 103 as being obvious over Leobandung U.S. Pat. 10,586,853, hereafter Leobandung, in view of Fung, U.S. Pat. Pub. 2023/0378260, hereafter Fung.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claims 21 and 26 (identical claims), Leobandung discloses everything as applied above.
Leobandung fails to explicitly disclose further comprising:
forming a fin spacer layer [128] adjacent to the stack structure [104]; and
removing a portion of the fin spacer layer by the etching process, such that a bottom surface of the S/D recess is higher than a bottom surface of the fin spacer layer.
However, Fung discloses (Fig. 2, see Figs 2A-2, 2B-2, par. [0034])
forming a fin spacer layer [128] adjacent to the stack structure; and
removing a portion of the fin spacer layer by the etching process, such that a bottom surface of the S/D recess [130] is at a same level as a bottom surface of the fin spacer layer [128’] (see Fig. 2B-2)
while Fung fails to explicitly teach wherein a bottom surface of the S/D recess is higher than a bottom surface of the fin spacer layer [128’], the ranges touch. Theref9re, this limitation is considered to be obvious over Fung (MPEP, 2144.05.I, and case law therein).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the method of Leobandung with the teachings of Fin spacer layers and etching the fin spacer layers of Fung, because Fung teaches (par. [0031]) that such fin spacers constraint lateral epitaxial growth of subsequently formed source/drain structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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