Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18478365 filed on 09/29/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-12 in the reply filed on 12/302025 is acknowledged.
Claims 21-28 have been added.
Allowable subject matter
Claims 4-5, 9, 12 are objected to as being dependent upon a rejected base claim (independent claims 1 & 10), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lavric et al. (US 2023/0420531) & Chai et al. (US 2017/0256544).
With respect to dependent claim 4, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein: the first n-type transistor, but not the second n-type transistor, includes the aluminum-free conductive layer between the first gate dielectric layer and the first gate electrode; and the second gate dielectric layer is in direct contact with the second gate electrode”.
With respect to dependent claim 5, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein: the second n-type transistor, but not the first n-type transistor, includes the aluminum-free conductive layer between the second gate dielectric layer and the second gate electrode; and the first gate dielectric layer is in direct contact with the first gate electrode”.
With respect to dependent claim 9, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a first p-type transistor disposed over the first n-type transistor, wherein the first p-type transistor includes: a third channel component; a third gate dielectric layer disposed over the third channel component, wherein the third gate dielectric layer is undoped; and a third gate electrode disposed over the third gate dielectric layer, wherein the third gate electrode is in direct contact with the third gate dielectric layer; and a second p-type transistor disposed over the second n-type transistor, wherein the second p-type transistor includes: a fourth channel component; a fourth gate dielectric layer disposed over the fourth channel component, wherein the fourth gate dielectric layer is doped with the p-type dipole material; and a fourth gate electrode disposed over the fourth gate dielectric layer, wherein the fourth gate electrode is in direct contact with the fourth gate dielectric layer”.
With respect to dependent claim 12, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the first p-type transistor and the second p-type transistor are not circumferentially surrounded by the conductive layer, and wherein one of the first n-type transistor or the second n-type transistor, but not both, is circumferentially surrounded by the conductive layer.”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 23-25, 27-28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lavric et al. (US 2023/0420531).
Regarding Independent claim 1, Lavric et al. teach a device, comprising:
a first n-type transistor (Fig. 1B, element 136A, paragraph 0043) that includes:
a first channel component (Fig. 1B, element 138, paragraph 0042);
a first gate dielectric layer (Fig. 1B, element 144A, paragraph 0043) disposed over the first channel component, wherein the first gate dielectric layer is undoped (paragraph 0043); and
a first gate electrode (Fig. 1B, element 148, paragraph 0043) disposed over the first gate dielectric layer; and
a second n-type transistor (Fig. 1B, element 136B, paragraph 0043) that includes:
a second channel component (Fig. 1B, element 138, paragraph 0042);
a second gate dielectric layer (Fig. 1B, element 144B, paragraph 0043) disposed over the second channel component, wherein the second gate dielectric layer is doped with a p-type dipole material (paragraph 0043); and
a second gate electrode (Fig. 1B, element 148, paragraph 0043) disposed over the second gate dielectric layer;
wherein at least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer (Fig. 1B, element 146B, paragraph 0043, 0028 discloses work function layer can comprise of TiN), and wherein the aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode (Fig. 1B).
Regarding claim 2, Lavric et al. teach wherein: the first gate dielectric layer circumferentially wraps around the first channel component in a cross-sectional side view (Fig. 1B); the first gate electrode circumferentially wraps around the first gate dielectric layer in the cross-sectional side view (Fig. 1B); the second gate dielectric layer circumferentially wraps around the second channel component in the cross-sectional side view (Fig. 1B); the second gate electrode circumferentially wraps around the second gate dielectric layer in the cross-sectional side view (Fig. 1B); and the first gate electrode or the second gate electrode circumferentially wraps around the aluminum-free conductive layer in the cross-sectional side view (Fig. 1B).
Regarding claim 3, Lavric et al. teach wherein: the first n-type transistor includes a first aluminum-free conductive layer (Fig. 1B, element 146B, paragraph 0043, 0028 discloses work function layer can comprise of TiN) between the first gate dielectric layer and the first gate electrode; and the second n-type transistor includes a second aluminum-free conductive layer (Fig. 1B, element 146B, paragraph 0043, 0028 discloses work function layer can comprise of TiN) between the second gate dielectric layer and the second gate electrode.
Regarding claim 6, Lavric et al. teach wherein the aluminum-free conductive layer is also free of p-type materials (paragraph 0043, 0028 discloses work function layer can comprise of TiN).
Regarding claim 7, Lavric et al. teach wherein the aluminum-free conductive layer includes titanium nitride (paragraph 0043, 0028 discloses work function layer can comprise of TiN).
Regarding Independent claim 23, Lavric et al. teach a device comprising:
a first complementary field effect (CFET) device (paragraph 0029, Fig. 1B, elements 134A, 136A) that includes:
a first semiconductive channel (Fig. 1B, element 138, paragraph 0042);
a first gate dielectric (Fig. 1B, element 144A, paragraph 0043) wrapping around the first semiconductive channel, wherein the first gate dielectric contains an undoped dielectric (paragraph 0043);
a first aluminum-free conductive layer (Fig. 1B, element 146B, paragraph 0043, 0028 discloses work function layer can comprise of TiN) wrapping around the first gate dielectric; and
a first gate electrode (Fig. 1B, element 148, paragraph 0043) wrapping around the first aluminum-free conductive layer; and
a second CFET device (paragraph 0029, Fig. 1B, elements 134B, 136B) that includes:
a second semiconductive channel (Fig. 1B, element 138, paragraph 0042);
a second gate dielectric (Fig. 1B, element 144B, paragraph 0043) wrapping around the second semiconductive channel, wherein the second gate dielectric contains with a p-type dipole material (paragraph 0043);
a second aluminum-free conductive layer (Fig. 1B, element 146B, paragraph 0043, 0028 discloses work function layer can comprise of TiN) wrapping around the second gate dielectric; and
a second gate electrode (Fig. 1B, element 148, paragraph 0043) wrapping around the second aluminum-free conductive layer.
Regarding claim 24, Lavric et al. teach wherein the first aluminum-free conductive layer or the second aluminum-free conductive layer is free of a p-type material (paragraph 0043, 0028 discloses work function layer can comprise of TiN).
Regarding claim 25, Lavric et al. teach wherein the first aluminum-free conductive layer or the second aluminum-free conductive layer contains titanium nitride (paragraph 0043, 0028 discloses work function layer can comprise of TiN).
Regarding claim 27, Lavric et al. teach the first semiconductive channel, the first gate dielectric, the first aluminum-free conductive layer, and the first gate electrode are portions of a first n-type transistor of the first CFET device (Fig. 1B, paragraph 0029); and the second semiconductive channel, the second gate dielectric, the second aluminum-free conductive layer, and the second gate electrode are portions of a second n-type transistor of the second CFET device (Fig. 1B, paragraph 0029).
Regarding claim 28, Lavric et al. teach he first CFET device further includes a first p-type transistor (Fig. 1B, element 134A, paragraph 0042) disposed directly over the first n-type transistor; and the second CFET device further includes a second p-type transistor (Fig. 1B, element 134B, paragraph 0042) disposed directly over the second n-type transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lavric et al. (US 2023/0420531).
Regarding claim 8, Lavric et al. teach wherein: the first gate dielectric layer has a first thickness; the second gate dielectric layer has a second thickness; the aluminum-free conductive layer has a third thickness; a ratio between the third thickness and the first thickness is in a range between about 0.1:1 and about 5:1; and a ratio between the third thickness and the second thickness is in a range between about 0.1:1 and about 5:1 (paragraph 0026, 0048, 0063 discloses that the thickness of various layer can vary. Furthermore, it is known in the art to vary the thickness of the gate dielectric thickness and work function layer with the motivation to optimize the threshold voltage, Accordingly, the thickness is an art recognized optimizable parameter. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at claim 8 limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 26, Lavric et al. teach wherein:the first gate dielectric has a first thickness; the second gate dielectric has a second thickness; the first aluminum-free conductive layer has a third thickness; the second aluminum-free conductive layer has a fourth thickness; a ratio between the third thickness and the first thickness is in a range between about 0.1:1 and about 5:1; and a ratio between the fourth thickness and the second thickness is in a range between about 0.1:1 and about 5:1 (paragraph 0026, 0048, 0063 discloses that the thickness of various layer can vary. Furthermore, it is known in the art to vary the thickness of the gate dielectric thickness and work function layer with the motivation to optimize the threshold voltage, Accordingly, the thickness is an art recognized optimizable parameter. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at claim 8 limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chai et al. (US 2017/0256544).
Regarding independent claim 10, Chai et al. teach a device, comprising:
a first vertical stack of transistors (Figs. 1-10, elements P_T1 & N_T4, paragraph 0026, 0093),
wherein the first vertical stack of transistors includes a first n-type transistor (Figs. 1-10, element N_T4, paragraph 0093) and a first p-type transistor (Figs. 1-10, element P_T1, paragraph 0026);
a second vertical stack of transistors (Figs. 1-10, elements P_T2 & N_T2, paragraph 0026, 0093), wherein the second vertical stack of transistors includes a second n-type transistor (Figs. 1-10, element N_T2, 0093) and a second p-type transistor (Figs. 1-10, element P_T2, paragraph 0026);
wherein: the first n-type transistor and the first p-type transistor include undoped gate dielectric layers (Figs. 1-10, elements P_GO1 & N_GO4, paragraph 0042-0045, 0141-0143);
the second n-type transistor and the second p-type transistor include doped gate dielectric layers (Figs. 1-10, elements P_GO2 & N_GO2, paragraph 0052-0057, 0121-0123);
at least one of the first n-type transistor or the second n-type transistor, is circumferentially surrounded by a conductive layer (Figs. 1-10, element N_BM2, paragraph 0119, 0106 discloses that barrier layer can be formed of TiN) that is free of a dipole material; and
an n-type metal gate electrode (Figs. 1-10, element N_CM2, paragraph 0119) circumferentially surrounds the conductive layer.
Regarding claim 21, Chai et al. teach the first vertical stack of transistors is a part of a first complementary field effect (CFET) device (Figs. 1-10); the second vertical stack of transistors is a part of a second CFET device (Figs. 1-10); and one of the first CFET device or the second CFET device, but not both, has a dipole drive-in (Figs. 1-10).
Regarding claim 22, Chai et al. teach a bottom surface of the first p-type transistor extends to an upper surface of the first ntype transistor (Figs. 1-13); and a bottom surface of the second p-type transistor extends to an upper surface of the second n-type transistor (Figs. 1-13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chai et al. (US 2017/0256544) in view of Lavric et al. (US 2023/0420531).
Regarding claim 11, Chai et al. teach the conductive layer is free of aluminum and contains titanium nitride (Figs. 1-10, element N_BM2, paragraph 0119, 0106 discloses that barrier layer can be formed of TiN).
Chai et al. do not explicitly disclose wherein: the doped gate dielectric layers are doped with aluminum.
Lavric et al. teach a semiconductor device compring n-type transistors with gate dielectric layers comprising dipole doped with aluminum (paragraph 0028, 0043).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chai et al. according to the teachings of Lavric et al. with the motivation to optimize the threshold voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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