DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 04/02/2026. Claims 1-3, 5-8 and 10-20 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 04/02/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIMIZU et al (US 2019/0296146 A1; hereafter SHIMIZU).
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Regarding claim 1. SHIMIZU discloses a structure comprising:
a silicon carbide (SiC) channel ( Fig 3, “The p-well region 16 functions as a channel region”, Para [0127]) horizontally between a source (Fig 3, left n+ region 18, Para [ 0028]) and a drain drift region (Fig 3, right n+ region 18, Para [ 0028]), and over a lower drift region ( n type region 14) such that a lower surface of the SiC channel ( Fig 3, “The p-well region 16 functions as a channel region”, Para [0127]) interfaces with an upper surface of the lower drift region ( n type region 14), wherein the SiC channel (Fig 3, “The p-well region 16, Para [ 0028]) has opposite doping from the source (Fig 3, left n+ region 18, Para [ 0028]) and the drain drift region ( Fig 3, right n+ region 18, Para [ 0028]); and
a capping semiconductor (Fig 3, region 60 is p-type silicon carbide, Para [ 0055]) on the SiC channel (Fig 3, “The p-well region 16, Para [ 0028]) and horizontally between the source (Fig 3, left n+ region 18, Para [ 0028]) and the drain drift region (Fig 3, right n+ region 18, Para [ 0028]), wherein the capping semiconductor (Fig 3, region 60 is p-type silicon carbide, Para [ 0055]) includes a semiconductor having a higher charge carrier mobility (Fig 3, “nitrogen region 60 is, for example, 1×10.sup.17 cm.sup.−3 or more and 1×10.sup.22 cm.sup.−3 or less”, Para [ 0064]) than the SiC channel ( Fig 3, “p-type impurity in the p-well region 16 is, for example, 5×10.sup.15 cm.sup.−3 or more and 1×10.sup.17 cm.sup.−3 or less”, Para [ 0037]), and a gate structure (Fig 3, gate structure [28,30], Para [ 0045]) is on the capping semiconductor (Fig 3, region 60 in the p-well region 16 is p-type silicon carbide, Para [ 0055]).
Regarding claim 2. SHIMIZU discloses the structure of claim 1, SHIMIZU further discloses wherein the capping semiconductor comprises crystalline silicon (Si) (Para [ 0057]).
Regarding claim 3. SHIMIZU discloses the structure of claim 1, SHIMIZU further discloses wherein the drain drift region (Fig 3, right n+ region 18, Para [ 0028]) is within a vertical junction field effect transistor (FET) structure (Fig 3, structure 10, Para [ 0158]) having a drain terminal (drain electrode 36, Para [ 0116]) below the drain drift region (Fig 3, right n+ region 18, Para [ 0028]).
Regarding claim 5. SHIMIZU discloses the structure of claim 1, SHIMIZU further discloses wherein the capping semiconductor (Fig 3, region 60 is p-type silicon carbide, Para [ 0055]) is vertically interposed between the SiC channel (Fig 3, “The p-well region 16, Para [ 0028]) and the gate structure (Fig 3, gate structure [28,30], Para [ 0045]).
Regarding claim 6. SHIMIZU discloses the structure of claim 1, SHIMIZU further discloses wherein the source (Fig 3, left n+ region 18, Para [ 0028]) includes the capping semiconductor thereon (Fig 3, region 60 is p-type silicon carbide, Para [ 0055]), and the drain drift region (Fig 3, at least portion of right n+ region 18, Para [ 0028]) is free of the capping semiconductor b(Fig 3, region 60 is p-type silicon carbide, Para [ 0055]).
Regarding claim 7. SHIMIZU discloses the structure of claim 1, SHIMIZU further discloses wherein a vertical thickness of the capping semiconductor is at most approximately ten nanometers (nm) (Para [ 0064] discloses “nitrogen region 60 is, for example, 1.5 nm or more and 5 nm or less”).
Allowable Subject Matter
Claims 8 and 10-15 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a capping semiconductor on the first channel and horizontally between the first source and the drain drift region, wherein the capping semiconductor is free of carbon (C) and includes crystalline silicon (Si), and the capping semiconductor is vertically interposed between the first channel and the gate structure, as recited in claim 8.
Claims 10-15 are allowed based on the dependency of claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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