DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Application
In response to Office action mailed 12/31/2025, Applicants amended claims 1, 6 and 15 in the response filed 03/30/2026.
Claim(s) 1-20 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub 2020/0219783; hereinafter Kim) in view of Yu et al. (PG Pub 2017/0170155; hereinafter Yu).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 9 (provided above and Fig. 10, Kim teaches a method of manufacturing a semiconductor device 10a, the method comprising:
bonding a first die 120 to a first side (top) of a substrate (annotated “substrate” in Fig. 9 above);
forming a stress buffer structure 310 over the first die (see Fig. 9), wherein the stress buffer structure comprises:
a first portion (top) of a first via (annotated “via” in Fig, 9 above) extending through a first insulating layer (annotated “ins-1”);
a second portion (middle) of the first via extending through a second insulating layer (annotated “ins-2”); and
a third portion (bottom) of the first via extending through a third insulating layer (annotated “ins-3”),
wherein the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via (see Fig. 9), and
wherein a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via (see Fig. 9); and
depositing a metal layer (annotated “metal layer”) over the stress buffer structure (see Fig. 9); and
coupling a heat spreader 290 to a top surface of the metal layer (see Fig. 9).
Although, Kim teaches bonding the first die 120 to a first side (top) of a substrate, he does not explicitly teach “bonding a second die to a first side of a substrate” or that “the heat spreader overlaps the entirety of the stress buffer structure.”
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In the same field of endeavor, refer to Fig. 16-provided above (being considered with a 180-degree rotation), Yu teaches a semiconductor device comprising: bonding a first die 107 and a second die 109 to a first side (top) of a substrate 301; and a heat spreader 1601 overlaps the entirety of a stress buffer structure 309 (see Fig. 16).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a second die into the semiconductor device of Kim, as taught by Yu, to provide a more robust package.
Furthermore, extending the heat spreader across the entire stress buffer layer, as taught by Yu, would increase heat dissipation from the device.
Regarding claim 4, refer to the figures cited above, Kim and Yu teach the diameter of the second portion of the first via (via in ins-2) decreases in a vertical direction from a top surface of the stress buffer structure (top of 310) towards a bottom surface of the stress buffer structure (decreases toward the mid-point of the via) (see Fig. 9).
Regarding claim 5, refer to the figures cited above, Kim and Yu teach before forming the stress buffer structure 310-Kim over the first die 120-Kim and the second die 109-Yu, forming a molding material 401-Yu over and around each of the first die and the second die (see Fig. 4); and performing a planarization process (para [0043]-Yu) to expose top surfaces of the first die and the second die (see Fig. 4-Yu).
Regarding claim 6, refer to the figures cited above, Kim and Yu teach the first die 120-Kim is thermally coupled to the heat spreader through the first via (“via”) and the metal layer (see Fig. 9), and the first via is in physical contact with a top surface of the first die.
Regarding claim 7, refer to the figures cited above, Kim and Yu teach the stress buffer structure (310-Kim and 500-Yu) has a thickness that is up to 100 µm (para [0045 and 0061]-Yu; teach 501 and 507 are at least 12µm combined, by extrapolating this to the additional layers one of ordinary skill in the art can deduce that the stress buffer structure has a thickness that is up to 100 µm.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Yu, as applied to claim 1 above, and further in view of Liu et al. (PG Pub 2017/0110421; hereinafter Liu).
Regarding claim 2, refer to the figures cited above, in the combination of Kim and Yu, Kim teaches the first insulating layer (“ins-1”), the second insulating layer (“ins-2”) and the third insulating layer (“ins-3”) (see Fig. 9). Kim does not teach the material composition of the insulating layers as comprising a low-temperature polyimide (LTPI) material.
In the same field of endeavor, refer to Fig. 5b- provided above, Liu teaches a redistribution layer 500 comprising: a first insulating layer 503, a second insulating layer 507 and a third insulating layer 511; wherein the first, second and third insulating layers comprise a low-temperature polyimide (LTPI) material (para [0051-0077]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the insulating layers of Kim, comprise the low-temperature polyimide, as taught by Liu, to “improve the interface adhesion between the first redistribution layer 505 and overlying layers” (para [0050]).
Regarding claim 3, refer to the figures cited above, in the combination of Kim and Yu in view of Liu, Although, Kim teaches the first via he is silent as to the material composition of the via comprising copper. Liu teaches a first via 505 comprises copper (para [0047]). One of ordinary skill in the art would use copper for the via, as taught by Liu, for its strong electrical properties.
Claim(s) 15-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (PG Pub 2021/0050295; hereinafter Tsai) and Kim et al. (PG Pub 2020/0219783; hereinafter Kim).
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Regarding claim 15, refer to Fig. 5a through Fig. 5H (Examiner’s mark-up of Fig. 5h provided above), Tsai teaches a package 504 comprising:
a top die 50-top bonded 510 to a bottom die 50-bottom;
a molding compound 310 surrounding the top die (see Fig. 5h);
a first stress buffer layer 206 over the top die, the first stress buffer layer comprising a plurality of first vias 218 extending through a first dielectric material 212 (see Fig. 5h), wherein a first one of the plurality of first vias is in physical contact with a substrate 52 of the top die, and wherein the substrate comprises silicon (para [0014]).
Tsai does not explicitly teach “a width of the bottom die is greater than a width of the top die.”
However, one of ordinary skill in the art would have found it obvious to alter the size (i.e. width) of the bottom die to be less than, equal to, or greater than the width of the top die since the court has held changes in size normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144). Furthermore, one of ordinary skill in the art would appreciate that changing the width of the dies would not change the functionality of the device, it is a mere design choice. According to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), see Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and see In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Tsai does not teach “a second stress buffer layer over the first stress buffer layer, the second stress buffer layer comprising a plurality of second vias extending through a second dielectric material, wherein each of the plurality of second vias overlaps and is in physical contact with a respective one of the plurality of first vias; and a heat spreader over and thermally coupled (via 280a) to the plurality of first vias and the plurality of second vias.”
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 9 (provided above and Fig. 10, Kim teaches a method of manufacturing a semiconductor device 10a, the method comprising: a first stress buffer layer (“ins-3” and vertical portion of RDL within this layer) over the top die (see Fig. 9), the first stress buffer layer comprising a plurality of first vias (vertical portion of RDL within “ins-3”) extending through a first dielectric material (see Fig. 9); a second stress buffer layer (“ins-2” and vertical portion of RDL within this layer) over the first stress buffer layer, the second stress buffer layer comprising a plurality of second vias (vertical portion of RDL within “ins-2”) extending through a second dielectric material (see Fig. 9), wherein each of the plurality of second vias overlaps and is in physical contact with a respective one of the plurality of first vias (see Fig. 9); and a heat spreader 290 over and thermally coupled (via 280a) to the plurality of first vias and the plurality of second vias (see Fig. 9).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the multi-layer stress-buffer layer, of Kim, in lieu of the stress-buffer layer of Tsai, to aid in electrical signal transmission.
Regarding claim 16, refer to the figures cited above, in the combination of Tsai and Kim, Kim teaches a third stress buffer layer (“ins-1” and vertical portion of RDL within this layer) over the second stress buffer layer (see Fig. 9), the third stress buffer layer comprising a plurality of third vias (vertical portion of RDL within “ins-1”) extending through a third dielectric material (“ins-1”), wherein a portion of each of the plurality of third vias overlaps and is in physical contact with a respective one of the plurality of second vias (see Fig. 9).
Regarding claim 17, refer to the figures cited above, in the combination of Tsai and Kim, Kim teaches a metal layer (“metal layer”) disposed between the third stress buffer layer (“ins-1) and the heat spreader 290, wherein the metal layer is in physical contact with top surfaces of the plurality of third vias (see Fig. 9).
Regarding claim 20, refer to the figures cited above, in the combination of Tsai and Kim, Kim teaches a diameter of each of the plurality of second vias (vias in the “ins-2”) decreases in a vertical direction from a top surface of the second stress buffer layer towards a bottom surface of the second stress buffer layer (see Fig. 9).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai and Kim, as applied to claim 16 above, and further in view of Liu et al. (PG Pub 2017/0110421; hereinafter Liu).
Regarding claim 19, refer to the figures cited above, in the combination of Tsai and Kim, Kim teaches the first dielectric material (“ins-3”), the second dielectric material (“ins-2”), and the third dielectric material (“ins-1”), he does not teach the material composition of the three dielectric layers as comprising a low-temperature polyimide (LTPI) material.
In the same field of endeavor, refer to Fig. 5b- provided above, Liu teaches a redistribution layer 500 comprising: a first insulating layer 503, a second insulating layer 507 and a third insulating layer 511; wherein the first, second and third insulating layers comprise a low-temperature polyimide (LTPI) material (para [0051-0077]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the insulating layers of Kim, comprise the low-temperature polyimide, as taught by Liu, to “improve the interface adhesion between the first redistribution layer 505 and overlying layers” (para [0050]).
Allowable Subject Matter
5. Claims 8-14 are allowable.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 8, a first die over and bonded to a first side of a second die; an encapsulant around the first die; and a stress buffer structure over the first die and the encapsulant, wherein the stress buffer structure comprises: a plurality of insulating layers; and a plurality of first vias, wherein each first via of the plurality of first vias extends through the plurality of insulating layers, wherein the plurality of first vias comprise copper, and a percentage ratio of a total volume of copper of the plurality of first vias to a total volume of the stress buffer structure is in a range from 10 to 30 percent. Claims 9-14 would be allowable, because they depend on allowable claim 8.
Claim 18 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 18, the plurality of first vias, the plurality of second vias, and the plurality of third vias comprise copper, and a percentage ratio of a total volume of copper of the plurality of first vias, the plurality of second vias, and the plurality of third vias to a total volume of the first stress buffer layer, the second stress buffer layer, and the third stress buffer layer is in a range from 10 to 30 percent.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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