DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/02/2023, 09/10/2024 and 01/14/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 02/05/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/05/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2020/0295129 (hereinafter Kinoshita).
Regarding Claim 1, Kinoshita discloses a semiconductor device, comprising:
a body of semiconductor material comprising:
a substrate (1, Fig. 2);
a first semiconductor region (2) over the substrate and comprising a first conductivity type; and
a second semiconductor region (5) over the first semiconductor region and comprising the first conductivity type;
wherein:
the second semiconductor region provides a first side of the body of semiconductor and the substrate provides a second side of the body of semiconductor material opposite to the first side (Figs. 1 & 2);
a trench gate structure comprising:
a trench (10) extending into the second semiconductor region from the first side;
a gate conductor (10) in the trench; and
a gate dielectric (9) separating the gate conductor from the second semiconductor region;
a first elongate stripe doped region (3a) of a second conductivity type opposite to the first conductivity type in the first semiconductor region, wherein the first elongate stripe doped region and the first semiconductor region provide a first charge-balance region; and
a second elongate stripe doped region (3b) of the second conductivity type in the second semiconductor region and interposed between the trench gate structure and the first elongate stripe doped region, wherein the second elongate stripe doped region and the second semiconductor region provide a second a second charge-balance region;
wherein:
the second elongate stripe doped region is orthogonal to the first elongate stripe doped region in a top view (Fig. 4); and
the second elongate stripe doped region is self-aligned to the trench gate structure (Fig. 2).
Regarding Claim 2, Kinoshita discloses the semiconductor device of Claim 1, wherein:
the second elongate stripe doped region contacts the first elongate stripe doped region below the trench gate structure (Fig. 2).
Regarding Claim 3, Kinoshita discloses the semiconductor device of Claim 1, wherein:
the first charge-balance region comprises a first plurality of elongate stripe doped regions within the first semiconductor region including the first elongate stripe doped region (Fig. 3);
the second charge-balance region comprises a second plurality of elongate stripe doped regions in the second semiconductor region including the second elongate stripe doped region (Fig. 4); and
the second plurality of elongate stripe doped regions is orthogonal to the first plurality of elongate stripe doped regions in the top view (Fig. 4).
Regarding Claim 4, Kinoshita discloses the semiconductor device of Claim 1, wherein: the first semiconductor region comprises SiC [0034].
Regarding Claim 5, Kinoshita discloses the semiconductor device of Claim 1, wherein: the second semiconductor region comprises SiC [0035].
Regarding Claim 6, Kinoshita discloses the semiconductor device of Claim 1, further comprising:
a doped region (5) comprising the first conductivity type within the body of semiconductor material where the first elongate stripe doped region and the second elongate stripe doped region intersect in the top view.
Regarding Claim 9, Kinoshita discloses the semiconductor device of Claim 1, further comprising:
a body region of the second conductivity type (6) within the second semiconductor region adjacent to the trench gate structure; and
a source region (7) of the first conductivity type within the body region;
wherein:
the first elongate stripe doped region and the second elongate stripe doped region are coupled to the source region (Fig. 2).
Regarding Claim 11, Kinoshita discloses a semiconductor device, comprising:
a body of semiconductor material comprising:
a substrate (Fig. 2, 1);
a first semiconductor region (2) over the substrate and comprising a first conductivity type; and
a second semiconductor region (5) over the first semiconductor region and comprising the first conductivity type;
wherein:
the second semiconductor region comprises a first side of the body of semiconductor and the substrate comprises a second side of the body of semiconductor material opposite to the first side (Fig. 2);
a trench gate structure comprising:
a trench extending into the second semiconductor region from the first side (Fig. 2);
a gate conductor (10) in the trench; and
a gate dielectric (9) separating the gate conductor from the second semiconductor region;
a first doped region (3a) of a second conductivity type opposite to the first conductivity type in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region; and
a second doped region (3b) of the second conductivity type in the second semiconductor region and interposed between the trench gate structure and the first doped region, wherein the second doped region and the second semiconductor region provide a second charge-balance region;
wherein:
the second doped region is self-aligned with the trench gate structure (Fig. 2).
Regarding Claim 12, Kinoshita discloses the semiconductor device of Claim 11, wherein:
the first doped region comprises a first elongate stripe doped region (Fig. 3);
the second doped region comprises a second elongate stripe doped region (Fig. 4); and
the second elongate stripe doped region is orthogonal to the first elongate stripe doped region in a top view (Fig. 4).
Regarding Claim 13, Kinoshita discloses the semiconductor device of Claim 12, further comprising:
a doped region (5) comprising the first conductivity type within the body of semiconductor material where the first elongate stripe doped region and the second elongate stripe doped region intersect in the top view.
Regarding Claim 14, Kinoshita discloses the semiconductor device of Claim 11, wherein:
the first semiconductor region and the second semiconductor region comprise SiC [0034]-[0035].
Regarding Claim 15, Kinoshita discloses the semiconductor device of Claim 11, further comprising:
a body region (7) of the second conductivity type within the second semiconductor region adjacent to the trench gate structure; and
a source region (7) of the first conductivity type within the body region;
wherein:
the first doped region and the second doped region are coupled to the source region (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kinoshita in further view of US Patent No. 11,462,638 to Hsieh (hereinafter Hsieh).
Regarding Claim 7, Kinoshita discloses the semiconductor device of Claim 1, wherein:
the trench comprises side walls and a lower side (Fig. 2); and
the gate dielectric comprises:
a first portion along the side walls of the trench and comprising a first thickness (Fig. 2)
Kinoshita does not disclose a second portion at the lower side of the trench which comprises a second thickness that is greater than the first thickness.
Hsieh discloses a vertical transistor having a gate dielectric which is thicker at a base of a trench compared to the sidewalls (Fig. 2A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the gate dielectric of Kinoshita such that a bottom portion is thicker than the sidewall portions. Gate dielectric thicknesses have known effects on the electric field surrounding the gate electrode. Among the reasons for having a thicker bottom portion for the gate dielectric, Hsieh notes that a reduction in switching loss can be achieved (Summary of the Invention)
Regarding Claim 8, Kinoshita discloses the semiconductor device of Claim 1 but does not show an embodiment wherein the second elongate stripe doped region is laterally inset with respect to the trench sidewalls in a cross-sectional view.
Hsieh discloses a trench comprises a sidewall in across-sectional view (Fig. 2A); and
the second elongate stripe doped region (215) is laterally inset with respect to the sidewall in the cross-sectional view.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the second elongate strip doped region such that it was laterally inset with respect to the sidewalls of the trench. Kinoshita is aware of the effects of the width of the second elongate strip doped region. It would therefore have been obvious to tailor the region based on desired performance, in particular with any shit in the thickness of the gate dielectric, as seen in Hsieh.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 requires the semiconductor device of Claim 1 to further comprise a doped region of the second conductivity type extending from the first side into the body of semiconductor material and contacting the first elongate stripe doped region. Kinoshita and Hsieh do not provide for such a structure. A search of other, relevant references in the art does not show Applicant’s invention to be obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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