Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 03/22/2023 ("03-22-23 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 03-22-23 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: STRUCTURE HAVING 2D CAPPING LAYER AND MANUFACTURING METHOD THEREOF
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Section 2173.02.I. of the MPEP provides the following guidance on how pre-issuance claims under examination are construed differently than patented claims:
Patented claims are not given the broadest reasonable interpretation during court proceedings involving infringement and validity, and can be interpreted based on a fully developed prosecution record. While "absolute precision is unattainable" in patented claims, the definiteness requirement "mandates clarity." Nautilus, Inc. v. Biosig Instruments, Inc., 527 U.S. __, 134 S. Ct. 2120, 2129, 110 USPQ2d 1688, 1693 (2014). A court will not find a patented claim indefinite unless the claim interpreted in light of the specification and the prosecution history fails to "inform those skilled in the art about the scope of the invention with reasonable certainty." Id. at 1689.
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The Office does not interpret claims when examining patent applications in the same manner as the courts. In re Packard, 751 F.3d 1307, 1312, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014); In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321-22 (Fed. Cir. 1989). The Office construes claims by giving them their broadest reasonable interpretation during prosecution in an effort to establish a clear record of what the applicant intends to claim. Such claim construction during prosecution may effectively result in a lower threshold for ambiguity than a court's determination. Packard, 751 F.3d at 1323-24, 110 USPQ2d at 1796-97 (Plager, J., concurring). However, applicant has the ability to amend the claims during prosecution to ensure that the meaning of the language is clear and definite prior to issuance or provide a persuasive explanation (with evidence as necessary) that a person of ordinary skill in the art would not consider the claim language unclear. In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)( claims are given their broadest reasonable interpretation during prosecution "to facilitate sharpening and clarifying the claims at the application stage"); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989).
Here, claim 3 is indefinite, because a parenthetic of (h-Bn, graphitic BN) may be construed as an exemplary claim language that includes examples or preferences which "...may lead to confusion over the intended scope of a claim." (see MPEP 2173.05(d)).
Claim 12 is indefinite, because the term “substantially” creates a zone of uncertainty around the limitation of “does not directly contact.”
A. Prior-art rejections based on Naylor
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2022/0415818 A1 to Naylor et al. ("Naylor").
Fig. 2A of Naylor has been provided to support the rejection below:
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Regarding independent claim 1, Naylor teaches a structure (see Fig. 2A for example) comprising:
a conductive region 220 (at level 202) (para [0033] - “IC device structure 200 includes an interconnect level 202”; para [0036] - “Interconnect structures within each of interconnect levels 202 and 203 have a graphene cap 250 over an interconnect metal 220.”) and a dielectric region 210 (at level 202) (para [0035] - “dielectric material 205”), wherein the conductive region 220 is disposed on or embedded in the dielectric region 210; and
a capping layer 250 (para [0036] - “graphene cap 250 may be referred to as two-dimensional (2D)”), disposed on the conductive region 220, wherein a material of the capping layer 250 comprises a 2D material (graphene).
Regarding claim 2, Naylor teaches the capping layer 250 that is in direct contact with the conductive region 220 and a material of the capping layer comprise copper.
Regarding claim 3, Naylor teaches the 2D material that comprises graphene.
Regarding claim 4, Naylor teaches a first insulating layer 205 (para [0034] - “dielectric material 205”), disposed on the dielectric region 210, wherein a top surface of the first insulating layer 205 and a top surface of the capping layer 250 are not coplanar.
Regarding claim 5, Naylor teaches the first insulating layer 205 that is further disposed on the capping layer 250.
Regarding claim 7, Naylor teaches a second insulating layer 210 (at level 203) (para [0038] - “dielectric material 210”), disposed on the first insulating layer 205 and the capping layer 250, and
a conductor 220 and/or 240 (at level 203) (para [0039] - “interconnect metal 220 and barrier layer 240”), penetrating through the second insulating layer 210 to being electrically connected to the conductive region 220.
Regarding claim 8, Naylor teaches wherein there is a contact interface between the first insulating layer 205 and the second insulating layer 210.
Regarding claim 9, Naylor teaches the capping layer 250 that is disposed and electrically connected between the conductive region 220 and the conductor 220 and/or 240.
Regarding claim 10, Naylor teaches the conductor 240 or 220, 240 that further penetrates through the capping layer 250.
Regarding independent claim 11, Naylor teaches a structure (see Fig. 2A for example) comprising:
a conductive region 220 (at level 202) (para [0033] - “IC device structure 200 includes an interconnect level 202”; para [0036] - “Interconnect structures within each of interconnect levels 202 and 203 have a graphene cap 250 over an interconnect metal 220.”) and a dielectric region 210 (at level 202) (para [0035] - “dielectric material 205”), wherein the conductive region 220 is disposed on or embedded in the dielectric region 210;
a capping layer 250 (para [0036] - “graphene cap 250 may be referred to as two-dimensional (2D)”), disposed on the conductive region 220; and
a first insulating layer 205 (para [0034] - “dielectric material 205”), disposed on the dielectric region 210, wherein a top surface of the first insulating layer 205 and a top surface of the capping layer 250 are not coplanar.
Regarding claim 12, Naylor teaches the first insulating layer 205 that does not directly contact a copper material 220 of the conductive region 220 substantially.
Regarding claim 13, Naylor teaches the first insulating layer 205 is further disposed on the capping layer 250.
Regarding claim 15, Naylor teaches a second insulating layer 210 (at level 203) (para [0038] - “dielectric material 210”), disposed on the first insulating layer 210 (at level 202) and the capping layer 250; and
a conductor 220 and/or 240 (at level 203) (para [0039] - “interconnect metal 220 and barrier layer 240”), penetrating through the second insulating layer 210 to being electrically connected to the conductive region 220.
Regarding claim 16, Naylor teaches wherein there is a contact interface between the first insulating layer 205 and the second insulating layer 210.
Regarding claim 17, Naylor teaches the capping layer 250 that is disposed and electrically connected between the conductive region 220 and conductor 220 and/or 240.
Regarding claim 18, Naylor teaches the conductor 240 or 220, 240 further penetrates through the capping layer 250.
Regarding independent claim 19, Naylor teaches a method comprising:
providing a structure comprising a conductive region 220 (at level 202) (para [0033] - “IC device structure 200 includes an interconnect level 202”; para [0036] - “Interconnect structures within each of interconnect levels 202 and 203 have a graphene cap 250 over an interconnect metal 220.”) and a dielectric region (at level 202), wherein the conductive region 220 is disposed on or embedded in the dielectric region 210 (at level 202) (para [0035] - “dielectric material 205”);
forming a capping layer 250 (para [0036] - “graphene cap 250 may be referred to as two-dimensional (2D)”) disposed on the conductive region 220, wherein a top surface of the first insulating layer 210 and a top surface of the capping layer 250 are not coplanar.
Regarding claim 20, Naylor teaches a material of the capping layer 250 that comprises a 2D material (graphene).
B. Prior-art rejections based on Hausmann
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0030062 A1 to Hausmann et al. ("Hausmann").
Fig. 2 of Hausmann has been provided to support the rejection below:
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Regarding independent claim 1, Hausmann teaches a structure comprising:
a conductive region 220A and a dielectric region 210 (para [0047] - “a first metal layer 220A formed in the first dielectric layer 210”; para [0048] - “For example, each of the first metal layer 220A and the neighboring first metal layer 220B includes copper.”), wherein the conductive region 220A is disposed on or embedded in the dielectric region 210; and
a capping layer 232 (para [0049] - “a selective graphene film 232”; para [0045] - “Further, the high-quality graphene can serve as a capping layer on top of the metal surface, which reduces resistance by reducing surface scattering.”), disposed on the conductive region 220A, wherein a material of the capping layer 232 comprises a 2D material (graphene).
Regarding claim 2, Hausmann teaches the capping layer 232 that is in direct contact with the conductive region 220A, and a material of the capping layer 232 that comprises copper.
Regarding claim 3, Hausmann teaches the 2D material that comprises graphene.
Regarding claim 4, Hausmann teaches a first insulating layer 230 (para [0051] - “the etch stop layer 230 includes a metal oxide. Examples of metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or combinations thereof.”), disposed on the dielectric region 210, wherein a top surface of the first insulating layer 230 and a top surface of the capping layer 232 that are no coplanar.
Regarding claim 5, Hausmann teaches the first insulating layer 230 that is further disposed on the capping layer 232.
Regarding claim 6, Hausmann teaches the first insulating layer 230 that comprises a first portion overlapping the capping layer 232 and a second portion not overlapping the capping layer 232, and a top surface of the first portion and a top surface of the second portion that are not coplanar.
Regarding claim 7, Hausmann teaches a second insulating layer 240 (para [0052] - “second dielectric layer 240”), disposed on the first insulating layer 230 and the capping layer 232; and
a conductor 270 and/or 262 (para [0053] - “…the second metal layer 270 may be lined with a second barrier layer 262.”), penetrating through the second insulating layer 240 to being electrically connected to the conductive region 220A.
Regarding claim 8, Hausmann teaches wherein there is a contact interface between the first insulating layer 230 and the second insulating layer 240.
Regarding claim 9, Hausmann teaches the capping layer 232 that is disposed and electrically connected between the conductive region 220A and conductor 270 and/or 262.
Regarding independent claim 11, Hausmann teaches a structure comprising:
a conductive region 220A and a dielectric region 210 (para [0047] - “a first metal layer 220A formed in the first dielectric layer 210”; para [0048] - “For example, each of the first metal layer 220A and the neighboring first metal layer 220B includes copper.”), wherein the conductive region 220A is disposed on or embedded in the dielectric region 210;
a capping layer 232 (para [0049] - “a selective graphene film 232”; para [0045] - “Further, the high-quality graphene can serve as a capping layer on top of the metal surface, which reduces resistance by reducing surface scattering.”), disposed on the conductive region 220A; and
a first insulating layer 230 (para [0051] - “the etch stop layer 230 includes a metal oxide. Examples of metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or combinations thereof.”), disposed on the dielectric region 210, wherein in a top surface of the first insulating layer 210 and a top surface of the capping layer 232 that are not coplanar.
Regarding claim 12, Hausmann teaches the first insulating layer 230 does not directly contact a copper material of the conductive region 220A substantially.
Regarding claim 13, Hausmann teaches the first insulating layer 230 that is further disposed on the capping layer 232.
Regarding claim 14, Hausmann teaches the first insulating layer 230 that comprises a first portion overlapping the capping layer 232 and a second portion not overlapping the capping layer 232, and a top surface of the first portion and a top surface of the second portion are not coplanar.
Regarding claim 15, Hausmann teaches a second insulating layer 240 (para [0052] - “second dielectric layer 240”), disposed on the first insulating layer 210 and the capping layer 232; and
a conductor 262 and/or 270 (para [0053] - “…the second metal layer 270 may be lined with a second barrier layer 262.”), penetrating through the second insulating layer 240 to being electrically connected to the conductive region 220A.
Regarding claim 16, Hausmann teaches wherein there is a contact interface between the first insulating layer 210 and the second insulating layer 240.
Regarding claim 17, Hausmann teaches the capping layer 232 that is disposed and electrically connected between the conductive region 220A and conductor 262 and/or 270.
Regarding independent claim 19, Hausmann teaches a method comprising:
providing a structure comprising a conductive region 220A and a dielectric region 210 (para [0047] - “a first metal layer 220A formed in the first dielectric layer 210”; para [0048] - “For example, each of the first metal layer 220A and the neighboring first metal layer 220B includes copper.”), wherein the conductive region 220A is disposed on or embedded in the dielectric region 210;
forming a capping layer 232 (para [0049] - “a selective graphene film 232”; para [0045] - “Further, the high-quality graphene can serve as a capping layer on top of the metal surface, which reduces resistance by reducing surface scattering.”) disposed on the conductive region 220A; and
forming a first insulating layer 230 (para [0051] - “the etch stop layer 230 includes a metal oxide. Examples of metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or combinations thereof.”) disposed on the dielectric region 210, wherein in a top surface of the first insulating layer 210 and a top surface of the capping layer 232 that are not coplanar.
Regarding claim 20, Hausmann teaches a material of the capping layer 232 that comprises a 2D material (graphene).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Patent. No. US 7,977,791 B2 to Chang et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817
10 December 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status