DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election with traverse of species B, figs. 1-15, claims 7-12 and 17-19, in the reply filed on 12/23/25 is acknowledged. The traversal is on the ground(s) that : Specifically, apart from a merely conclusory statement that such factors may exist, no distinct classifications or other field of search has been identified, absent which the record reflects that "the classification is the same and the field of search is the same and there is no clear indication of separate future classification and field of search" and, as such, "no reasons exist for dividing among independent or related inventions." This is not found persuasive because a different field of search is required such as employing different search strategies or search queries for a device comprising different locations of the conductive element (130) or different types of electrical connections between the MEMs and ASIC (e.g. bond wire vs. metal layer). The traversal is on the ground(s) that: Similarly, the Requirement asserts a serious examination burden, without the required "appropriate explanation of non-prior art issues under 35 U.S.C. 101 ... and/or 35 U.S.C. 112(a) relevant to one invention that are not relevant to the other invention." This is not found persuasive because the MPEP does not require a Restriction Requirement to set forth in the office action the “non-prior art issues under 35 U.S.C. 101 ... and/or 35 U.S.C. 112(a)”, as asserted by the Applicant. The requirement is still deemed proper and is therefore made FINAL. Claim s 1-6, 13-16 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/23/25. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 7, 12, 17 and 19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cachia, US Publication No. 2016/0090301 A1 . Cachia anticipates: 7. A chip package, comprising (see fig. 5 annotated below): an application chip (14 b ) having a conductive pad (e.g. “conductive pad” annotated ) ; a micro-electromechanical systems (MEMS) chip (12) located on the application chip, and comprising a MEMS structure (16/19) and a cap (17) covering the MEMS structure, wherein the MEMS structure (16/19) is located between the cap (17) and the application chip (14b) , and a surface of the cap (17) facing away from the application chip has a metal layer (e.g. “metal layer annotated”) ; a first conductive element (38) located on the conductive pad of the application chip; and a molding compound (e.g. “molding” annotated) located on the application chip (14b) , covering the metal layer (e.g. “metal layer annotated”) , and surrounding the MEMS chip (12) , wherein the first conductive element (38) is located in the molding compound. See Cachia at para. [000 1 ] – [00 45 ], figs. 1-5. 12. The chip package of claim 7, wherein said surface of the cap (17) has an isolation layer (e.g. “isolation layer” annotated) between the metal layer ( e.g. “metal layer annotated”) and said surface of the cap, fig. 5. Regarding claim 17: Cachia teaches the limitations as applied to claim 7 above. Cachia further teaches the added limitation: cutting the MEMS wafer to form at least one MEMS chip such that a conductive pad of the application wafer is exposed (e.g. see singulation at para. [00 38 ], fig. 2D) Regarding claim 19: Cachia teaches the limitations as applied to claim 12 above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 8-11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cachia, as applied to claims 7 and 17 above, in view of Liu et al., US Publication No. 2021/0032096 A1. Regarding claim 8: Cachia teaches all the limitations of claim 7 above, and further teaches: the chip package further comprises: (see fig. 5 above) a redistribution layer (e.g. “redistribution layer” annotated), wherein a first section (e.g. first section directly connected to 38) of the redistribution layer is electrically connected to the first conductive element (e.g. “conductive pad” annotated) in the molding compound (e.g. “molding compound” annotated), and extends (e.g. The first section of the redistribution layer is a three-dimensional object so it extends in all three directions.) to a surface of the molding compound facing away from the MEMS chip. Cachia does not expressly teach: wherein the molding compound has a through hole aligned with the first conductive element In an analogous art, Liu teaches: (see fig s . 1 and 6) wherein the molding compound (140) has a through hole (160 left ) aligned with the first conductive element (112) , and the chip package further comprises: a redistribution layer (170 left ) , wherein a first section (e.g. portion of 170 near 146/146T ) of the redistribution layer is electrically connected to the first conductive element (112) in the molding compound (140) , and extends to a surface of the molding compound (140) facing away from the MEMS chip (120). See Liu at para. [00 36 ] – [00 41 ], figs. 1 -6. Regarding claim 9: Cachia further teaches: 9. The chip package of claim 8, (see fig. 5 above) wherein a second section (e.g. second section directly below 46 in the middle) of the redistribution layer is electrically connected (e.g. cap 17 is silicon so electrically conductive) to the metal layer (e.g. “metal layer” annotated) and extends (e.g. The second section of the redistribution layer is a three-dimensional object so it extends in all three directions.) to said surface of the molding compound. Liu also teaches: 9. The chip package of claim 8, wherein a second section (e.g. portion of 170 directly below 190) of the redistribution layer (170 left) is electrically connected (e.g. through intervening 122, 120) to the metal layer (e.g. 170 right) and extends to said surface of the molding compound (140), fig. 6. Regarding claim 9: Cachia further teaches: 10. The chip package of claim 9, further comprising: a conductive structure (46) located on the second section (e.g. second section directly below 46 in the middle) of the redistribution layer , fig. 5. Liu also teaches: 10. The chip package of claim 9, further comprising: a conductive structure ( 190 ) located on the second section (e.g. portion of 170 directly below 190), figs. 1 and 6. Regarding claim 11: Cachia further teaches: 11. The chip package of claim 8, (see fig. 5 annotated) further comprising: a conductive structure (e.g. 46 directly above “metal layer” annotated) located on (e.g. located on the right side of) the first section (e.g. first section directly connected to 38) of the redistribution layer. Liu also teaches: 11. The chip package of claim 8, further comprising: a conductive structure (190) located on the first section (e.g. portion of 170 near 146/146T) of the redistribution laye r, figs. 1 and 6. Regarding claim 18: Cachia and Liu teach as applied to claims 8 and 9 above. Regarding claim s 8-11 and 18: MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103 indicates : “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397 . “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396 . Also see MPEP 2143, Examples of Basic Requirements of a Prima Facie Case of Obviousness, (I)(B): Simple Substitution of One Known Element for Another To Obtain Predictable Results . KSR Int’l Co. v. Teleflex Inc ., 127 S.Ct . 1727, 82 USPQ2d 1385 (2007). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Cachia with the teachings of Liu to substitute the wire bonding for a through hole connection because Liu teaches “… reliability of wire-bonding method is lower, and the wire-bonding method may occupy more volume of the chip package such as the height of a top of the wire. ” See Liu at para. [000 3 ] . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 23 March 2026