DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 7/1/26.
Applicant’s amendment to claims 1, 8, 17 and 18 is acknowledged.
Claims 1-6 and 13-16 are cancelled.
Claims 7-12 and 17-19 are pending and subject to examination at this time.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Weber, US 20140374917 A1 (e.g. In fig. 3, Weber teaches a MEMs substrate 320, cap substate 330 and an ASIC 310. In fig. 4, Weber teaches an ASIC 410 and a MEMs substrate 420.)
Response to Arguments
Applicant's arguments filed 7/1/26 have been fully considered but they are not persuasive.
In Cachia’s fig. 5, the bond wires (38) are not used to teach the redistribution layers, as asserted by the Applicant. The redistribution layers are the horizontal conductive layers annotated in fig. 5 below with arrows and highlighted by a box.
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In regards to the amended limitation, the region where the molding compound extends between the metal layer and the redistribution layer is annotated by a dashed arrow in fig. 5 above. Similar to how roof extends between the sidewalls of a house. Claim 1 does not require the molding compound to be on the same plane as the redistribution layer and/or metal layer. Similar to how a roof does not have to be on the same plane as the sidewalls to extend between the sidewalls. Also, claim 1 also does not require the molding compound to form an interface with the bottom surface of the redistribution layer and another interface with the top surface of the metal layer (e.g. see Applicant’s fig. 10)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7, 12, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cachia, US Publication No. 2016/0090301 A1.
Cachia anticipates:
7. A chip package, comprising (see fig. 5 annotated below):
an application chip (14b) having a conductive pad (e.g. “conductive pad” annotated) ;
a micro-electromechanical systems (MEMS) chip (12) located on the application chip, and comprising a MEMS structure (16/19) and a cap (17) covering the MEMS structure, wherein the MEMS structure (16/19) is located between the cap (17) and the application chip (14b), and a surface of the cap (17) facing away from the application chip has a metal layer (e.g. “metal layer annotated”);
a first conductive element (38) located on the conductive pad of the application chip; and
a molding compound (e.g. “molding” annotated) located on the application chip (14b), covering the metal layer (e.g. “metal layer annotated”), and surrounding the MEMS chip (12), wherein the first conductive element (38) is located in the molding compound; and
a redistribution layer (e.g. “redistribution layer” annotated and highlighted with box) located on the molding compound (e.g. “molding” annotated), wherein at least a portion of the molding compound extends between the metal layer and the redistribution layer (e.g. The region where the molding compound extends between the metal layer and the redistribution layer is annotated by a dashed arrow.) See Cachia at para. [0001] – [0045], figs. 1-5.
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12. The chip package of claim 7, wherein said surface of the cap (17) has an isolation layer (e.g. “isolation layer” annotated) between the metal layer (e.g. “metal layer annotated”) and said surface of the cap, fig. 5.
Regarding claim 17:
Cachia teaches the limitations as applied to claim 7 above.
Cachia further teaches the added limitation:
cutting the MEMS wafer to form at least one MEMS chip such that a conductive pad of the application wafer is exposed (e.g. see singulation at para. [0038], fig. 2D)
Regarding claim 19:
Cachia teaches the limitations as applied to claim 12 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cachia, as applied to claims 7 and 17 above, in view of Liu et al., US Publication No. 2021/0032096 A1.
Regarding claim 8:
Cachia teaches all the limitations of claim 7 above, and further teaches:
(see fig. 5 above) a first section (e.g. first section directly connected to 38) of the redistribution layer (e.g. “redistribution layer” annotated) is electrically connected to the first conductive element (e.g. “conductive pad” annotated) in the molding compound (e.g. “molding compound” annotated), and extends (e.g. The first section of the redistribution layer is a three-dimensional object so it extends in all three directions.) to a surface of the molding compound facing away from the MEMS chip.
Cachia does not expressly teach:
wherein the molding compound has a through hole aligned with the first conductive element
In an analogous art, Liu teaches:
(see figs. 1 and 6) wherein the molding compound (140) has a through hole (160 left) aligned with the first conductive element (112), and the chip package further comprises:
a redistribution layer (170 left), wherein a first section (e.g. portion of 170 near 146/146T) of the redistribution layer is electrically connected to the first conductive element (112) in the molding compound (140), and extends to a surface of the molding compound (140) facing away from the MEMS chip (120). See Liu at para. [0036] – [0041], figs. 1-6.
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Regarding claim 9:
Cachia further teaches:
9. The chip package of claim 8, (see fig. 5 above) wherein a second section (e.g. second section directly below 46 in the middle) of the redistribution layer is electrically connected (e.g. cap 17 is silicon so electrically conductive) to the metal layer (e.g. “metal layer” annotated) and extends (e.g. The second section of the redistribution layer is a three-dimensional object so it extends in all three directions.) to said surface of the molding compound.
Liu also teaches:
9. The chip package of claim 8, wherein a second section (e.g. portion of 170 directly below 190) of the redistribution layer (170 left) is electrically connected (e.g. through intervening 122, 120) to the metal layer (e.g. 170 right) and extends to said surface of the molding compound (140), fig. 6.
Regarding claim 9:
Cachia further teaches:
10. The chip package of claim 9, further comprising: a conductive structure (46) located on the second section (e.g. second section directly below 46 in the middle) of the redistribution layer, fig. 5.
Liu also teaches:
10. The chip package of claim 9, further comprising: a conductive structure (190) located on the second section (e.g. portion of 170 directly below 190), figs. 1 and 6.
Regarding claim 11:
Cachia further teaches:
11. The chip package of claim 8, (see fig. 5 annotated) further comprising: a conductive structure (e.g. 46 directly above “metal layer” annotated) located on (e.g. located on the right side of) the first section (e.g. first section directly connected to 38) of the redistribution layer.
Liu also teaches:
11. The chip package of claim 8, further comprising: a conductive structure (190) located on the first section (e.g. portion of 170 near 146/146T) of the redistribution layer, figs. 1 and 6.
Regarding claim 18:
Cachia and Liu teach as applied to claims 8 and 9 above.
Regarding claims 8-11 and 18:
MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103 indicates:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Also see MPEP 2143, Examples of Basic Requirements of a Prima Facie Case of Obviousness, (I)(B): Simple Substitution of One Known Element for Another To Obtain Predictable Results. KSR Int’l Co. v. Teleflex Inc., 127 S.Ct. 1727, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Cachia with the teachings of Liu to substitute the wire bonding for a through hole connection because Liu teaches “…reliability of wire-bonding method is lower, and the wire-bonding method may occupy more volume of the chip package such as the height of a top of the wire.” See Liu at para. [0003].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michele Fan/
Primary Examiner, Art Unit 2818
2 September 2026
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