DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 13-20 and 21-32) in the reply filed on 12/29/2025 s acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13, 17, 19, 21, 23-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Furusho (US 2024/0379709).
Regarding claim 13, Furusho discloses a method of manufacturing an integrated circuit device, the method comprising: providing a semiconductor body (Fig.5A, numeral 20W) having a first side and a second side opposite the first side (Fig. 5A); etching trenches (24a), (24b) in the first side, wherein the trenches form a grid (Fig, 5C, [0100]); depositing sacrificial material (Fig.5D, numeral m5) in the trenches from the first side; etching from the first side so as to recess the sacrificial material within the trenches and create first trench recesses (Fig.5E), wherein the first trench recesses have a first depth ([0101]); forming a first semiconductor structure (Fig.5F, numeral m5; Fig.7, numeral 62b; [0121]; note: 62b is polysilicon) in the semiconductor body by depositing a first semiconductor material (62) within the first trench recesses; thinning the semiconductor body from the second side (Fig.5J; [0104]); etching the sacrificial material from the second side so as to create second trench recesses (Fig.5L; [0105]), wherein the second trench recesses extend from the second side to the first semiconductor structure (Fig.5L); and depositing dielectric (Fig. 5N, numeral 52) in the second trench recesses ([0107]).
Regarding claim 17, Furusho discloses doping to form an array of photodiodes that are laterally separated by the trenches, wherein doping to form the array of photodiodes comprises forming P-wells that have a depth greater than or equal to the first depth (Fig.5C, numeral 22; [0085]).
Regarding claim 19, Furusho discloses wherein the first semiconductor material is polysilicon ([0121]; note: 62b is polysilicon) and the first depth is one fourth or less than a depth of the trenches (Fig. 5E; [0101]).
Regarding claim 21, Furusho discloses a method of forming an image sensor, comprising: providing a semiconductor substrate (Fig.5A, numeral 20W) having a first side and an opposite second side; forming trenches in the semiconductor substrate from the first side (Fig.5C, numerals 24a, 24b), wherein the trenches laterally separate regions of the semiconductor substrate corresponding to light sensing elements (Fig.4); filling the trenches with a removable fill material (Fig.5D, numeral m4); removing an upper portion of the removable fill material from the first side to form recessed regions while leaving remaining removable fill material at greater depth (Fig.5E); forming a semiconductor structure (Fig.5F, numeral m5; Fig.7, numeral 62b; [0121]; note: 62b is polysilicon )in the recessed regions such that the semiconductor structure overlies the remaining removable fill material and is vertically closer to the first side than the remaining removable fill material; thinning the semiconductor substrate from the second side (Fig.5J); removing the remaining removable fill material from the second side to reopen the trenches (Fig.5L); and forming an isolation structure in the reopened trenches from the second side (Fig.5N, numeral 52).
Regarding claim 23, Furusho discloses wherein the semiconductor structure has a crystal structure continuous with the semiconductor substrate (Fig.5B, numeral 20W).
Regarding claim 24, Furusho discloses forming a front side metal interconnect structure with an electrical connection to the semiconductor structure (Fig.7, numeral 30).
Regarding claim 25, Furusho discloses a method of manufacturing an integrated circuit device, the method comprising: providing a semiconductor substrate (Fig.5C, numeral 20W) having a first side and an opposite second side; etching trenches (Fig.5C, numerals 24a, 24b) in the first side, wherein the trenches form a grid; depositing sacrificial material (Fig.5D, numeral m3) in the trenches from the first side; etching from the first side so as to recess the sacrificial material within the trenches and create first trench recesses (Fig. 5E), wherein the first trench recesses have a first depth; depositing a second material (Fig.5F, numeral m5) in the first trench recesses and filling the first trench recesses, wherein the second material is distinct from the sacrificial material ([0102]); thinning the semiconductor substrate from the second side (Fig. 5J) ([0104]); etching the sacrificial material from the second side so as to create second trench recesses (Fig.5L) ([0105]), wherein the etch process stops on the second material (m5); and depositing dielectric in the second trench recesses (Fig.5N, numeral 52).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furusho as applied to claim 21 above, and further in view of Noda (US 2022/0344394).
Regarding claim 22, Furusho does not disclose thermally processing the semiconductor substrate to reduce defects created during a process of forming the trenches.
Noda however discloses processing the semiconductor substrate to reduce defects created during a process of forming the trenches ([0302]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Furusho with Noda to have thermally processing the semiconductor substrate to reduce defects created during a process of forming the trenches for the purpose reducing a dark current (Noda, [0302]).
Allowable Subject Matter
Claims 14-16, 18, 20, and 26-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest etching holes from the first side, wherein the holes extend part way through the first semiconductor structure and have a second depth; depositing a first dielectric in the holes; etching from the first side so as to recess the first dielectric within the holes and create hole recesses, which have a third depth; and depositing a second semiconductor material in the hole recesses as required by claim 14.
The search of the prior art does not disclose or reasonably suggest wherein forming the first semiconductor structure comprises epitaxial growth of the first semiconductor material within the first trench recesses as required by claim 18.
The search of the prior art does not disclose or reasonably suggest epitaxially growing semiconductor in the second trench recesses as required by claim 20.
The search of the prior art does not disclose or reasonably suggest
forming a mask) on the first side, wherein the mask covers first portions of the filled first trench recesses and defines openings over second portions of the filled first trench recesses as required by claim 26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891