DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/4/2023 and 7/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims Status
Claims 1-20 are currently pending and being examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the plurality of semiconductors" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, and consistency with claim 1, "the plurality of semiconductors" in line 2 will be interpreted to read as "the plurality of semiconductor dies".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 5-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM et al (US 2023/0197557 A1).
Re claim 1, Kim discloses in FIG. 4 (with references to FIGS. 2-3) a fan out package (400) comprising: a plurality of semiconductor dice (100a/100b/200a/200b; [0049]), each of the plurality of semiconductor dies (100a/100b/200a/200b) including a first surface (upper plane) and a second surface (lower plane) opposite to (below) the first surface (upper plane);
a redistribution layer (430; [0058]) coupled (electrically; [0057]) to the first surface (upper plane) of each of the plurality of semiconductor dies (100a/100b/200a/200b);
a dieback conductive member (440; [0058]) coupled (electrically; [0057]) to the second surface (lower plane) of each of the plurality of semiconductors dies (100a/100b/200a/200b); and
an encapsulation material (460; [0054]) coupled to (surrounds and contacts; [0054]) the plurality of semiconductor dies (100a/100b/200a/200b) and the dieback conductive member (440).
Re claim 3, Kim discloses the fan out package of claim 1, wherein the dieback conductive member (440) includes a plurality of conductive plates (electrodes 120/220; [0037]; [0041] and [0044]-[0045]), each of the plurality of conductive plates (electrodes 120/220) coupled (electrically connected) to a separate semiconductor die (100 for 120 and 220 for 200) of the plurality of semiconductor dies (100a/100b/200a/200b).
Re claim 5, Kim discloses the fan out package of claim 1, wherein the plurality of semiconductors (100a/100b/200a/200b) includes a first semiconductor die (100a), a second semiconductor die (100b), and a third semiconductor die (200a).
Re claim 6, Kim discloses the fan out package of claim 1, wherein the redistribution layer (430) includes a source contact pad (unseen portion) that is common (for 132 of 100a/100b and 230 of 200a/200b; [0040]; [0045]; [0050] and [0052]) to the plurality of semiconductor dies (100a/100b/200a/200b).
Re claim 7, Kim discloses the fan out package of claim 1, wherein the dieback conductive member (440) includes a drain contact pad (horizontal portion of 440) that is common (electrically connected; [0057]) to the plurality of semiconductor dies (100a/100b/200a/200b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2; 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yeung et al (US 2016/0260651 A1, hereafter Yeung).
Re claim 2, Kim discloses the fan out package of claim 1.
But, fails to disclose wherein the dieback conductive member (440) includes a single conductive spacer coupled to the plurality of semiconductor dies (100a/100b/200a/200b).
However,
Yeung discloses in FIG. 7 a power comprising wherein a dieback conductive member (8; [0070]) includes a single conductive spacer (copper; [0018]-[0019]) coupled to a plurality of semiconductor dies (2; [0052] and [0070]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim by substituting the dieback conductive member of Yeung for the dieback conductive member and first substrate assembly of Kim, to form a heat for electrical and thermal conduction, improving heat dissipation within the device, the dual function of the heat sink may allow a compact package to be provided (Yeung; Abstract; and [0012]).
Re claim 17, Kim and Yeung disclose he method of claim 16, wherein the dieback conductive member includes a single conductive spacer coupled to the plurality of semiconductor dies (see claim 2).
Claim 4; and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of GRASSMAN (US 2022/0230930 A, hereafter Grassman).
Re claim 4, Kim discloses the fan out package of claim 1.
Bu, Kim fails to disclose the fan out package further comprising: a passivation layer coupled to the plurality of semiconductor dies (100a/100b/200a/200b).
However,
Grassman discloses in FIG. 2 a power comprising a passivation layer (unlabeled structure under 112 surrounding pads 128/130; [0071] and [0074]) coupled to (contacting) a semiconductor die (110; [0067]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim by adding the passivation layer of Grassman, the passivation layer coupled to the plurality of semiconductor dies, providing isolation and selective positioning of the semiconductor die pads.
Re claim 20, Kim and Grassman disclose the method of claim 16, further comprising: forming a passivation layer on the first surface of each of the plurality of semiconductor dies (see claim 4).
Claims 8-10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al (US 2021/0057372 A1, hereafter Oh) in view of Kim.
Re claim 8, Oh discloses in FIG. 2 a power module (10) comprising:
a substrate (110; [0044]);
a first fan out package (122-123/100a/113; [0048] and [0050]) coupled (electrically connected) to the substrate (110); and
a second fan out package (124/100b/112-113; [0048] and [0050]) coupled (electrically connected) to the substrate (110), each of the first fan out package (122-123/100a/113) and the second fan out package (124/100b/112-113) including:
a semiconductor die (100a/100b; [0035] and [0050]), each of the semiconductor dies (100a/100b) including a first (lower for 100a and upper for 100b) surface and a second (upper or 100a and lower for 100b) surface opposite to the first (lower/upper) surface;
a redistribution layer (122-123 for 100a and 112-113 for 100b; [0048]) coupled (electrically connected) to the first (lower/upper) surface of each of the semiconductor dies (100a/100b);
a dieback conductive member (113 for 100a and 124 for 100b; [0048]) coupled (electrically connected) to the second (lower) surface of each of the semiconductors dies (100a/100b); and
an encapsulation material (140; [0056]) coupled to (physically contacting) the semiconductor dies (100a/100b) and the dieback conductive member (113 for 100a and 124 for 100b).
Oh fails to disclose each of the first fan out package (122-123/100a/113) and the second fan out package (124/100b/112-113) including: a plurality of semiconductor dies, each of the plurality of semiconductor dies including a first surface and a second surface opposite to the first surface; the redistribution layer (122-123 for 100a and 112-113 for 100b) coupled to the first surface of each of the plurality of semiconductor dies; the dieback conductive member (113 for 100a and 124 for 100b) coupled to the second surface of each of the plurality of semiconductors dies; and an encapsulation material (140) coupled to the plurality of semiconductor dies.
However,
Kim discloses power modules comprising: a plurality of semiconductor dies (100a to 100f; [0031]), connected in parallel ([0031]), and each of the plurality of semiconductor dies (100a to 100f) including a first (upper) surface and a second (lower) surface opposite to the first surface.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Oh by adding at least one additional semiconductor die of Kim to each of the each of the first fan out package and the second fan out package of Oh, producing a plurality of semiconductor dies, each of the plurality of semiconductor dies including a first surface and a second surface opposite to the first surface; the redistribution layer coupled to the first surface of each of the plurality of semiconductor dies; the dieback conductive member coupled to the second surface of each of the plurality of semiconductors dies; and an encapsulation material (140) coupled to the plurality of semiconductor dies, in order to increase the current capacity of each fan out package (Kim; [0031]).
Re claim 9, Oh discloses the power module of claim 8, wherein the substrate (110) is a first substrate, the power module (10) further comprising: a second substrate (120; [0048]), the first and second fan out packages (122-123/100a/113 and 124/100b/112-113) being disposed between and coupled (connected) to the first substrate (110) and the second substrate (120).
Re claim 10, Oh discloses the power module of claim 9, wherein the dieback conductive member (113 for 100a) of the first fan out package (122-123/100a/113) is coupled (electrically connected) to the first substrate (110), and the dieback conductive member (124 for 100b) of the second fan out package 124/100b/112-113 is coupled (electrically connected to the second substrate (120).
Re claim 15, Oh discloses the power module of claim 8, wherein the encapsulation material (140) is a first encapsulation material.
But, fails to disclose the power module (10) further comprising: a second encapsulation material coupled to the substrate (110), the first fan out package (122-123/100a/113), and the second fan out package (124/100b/112-113).
However, Kim would render these limitations obvious by disclosing a second encapsulation (490; [0109]) in the embodiment of FIG. 12 as a second mold coupled to the substrate (110), the first fan out package (122-123/100a/113), and the second fan out package (124/100b/112-113) for the final packaging of the power module, as part of the higher current capacity devices discussed for claim 8.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Oh and Kim as applied to claim 8, and further in view of Liang et al (US 2013/0020694 A1, hereafter Liang).
Re claim 11, Oh discloses the power module of claim 8.
But, fails to explicitly disclose the power module of claim 8, further comprising: a first lead frame portion disposed between and coupled to the first substrate (110) and the second substrate (120); and a second lead frame portion disposed between and coupled to the first substrate (110) and the second substrate (120).
However,
Liang discloses in FIG. 4 a power module comprising a first lead frame portion (334/346; [0032]) disposed between and coupled to the first substrate (416; [0032]) and the second substrate (414; [0032]) and a second lead frame portion (330/342; [0032]) disposed between and coupled to the first substrate (416) and the second substrate (414).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Oh by adding the first and second lead frame portions of Liang, the first lead frame portion disposed between and coupled to the first substrate (110) and the second substrate (120); and the second lead frame portion disposed between and coupled to the first substrate (110) and the second substrate (120), for establishing external connections for power modules with semiconductor devices connected both in series and in parallel for device operation (FIG. 1-2; [0027]; [0031] and [0044]).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh and Kim as applied to claim 8, and further in view of Muto et al (US 2008/0012045 A1, hereafter Muto).
Re claims 12-13, Oh and Kim disclose the power module of claim 8.
But, fail to disclose the power module further comprising: a clip member, the first and second fan out packages (122-123/100a/113 and 124/100b/112-113) disposed between and coupled to the substrate (110) and the clip member; and wherein the dieback conductive member (113 for 100a) of the first fan out package is coupled to the substrate (110), and the dieback conductive member (124 for 100b) of the second fan out package is coupled to the substrate (110).
However,
Muto discloses in FIG. 5 a power module comprising a clip member (20; [0097]), first and second fan out packages (18/16/17 and 18/15/17; [0097]) coupled by the clip (20).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Oh and Kim by adding the clip of Muto, resulting in the first and second fan out packages (122-123/100a/113 and 124/100b/112-113) disposed between and coupled to the substrate (110) and the clip member; and wherein the dieback conductive member (113 for 100a) of the first fan out package is coupled to the substrate (110), and the dieback conductive member (124 for 100b) of the second fan out package is coupled to the substrate (110), for establishing the parallel connections of Kim as part of the higher current capacity devices discussed for claim 8.
Re claim 14, Oh discloses the power module of claim 12, wherein the substrate (110) includes a first conductive layer (125; [0048]), a second conductive layer (122/123/124; [0048]), and a dielectric layer (121; [0048]) disposed between and coupled to the first conductive layer (125) and the second conductive layer (122/123/124).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Re claim 16, Kim discloses in FIGS. 5A-12 a method for manufacturing a fan out package, the method comprising:
applying an encapsulation material (460 in FIG. 6A; [0089]) to a plurality of semiconductor dies (100a/200a/200b/100b; [0089]);
coupling a dieback conductive member (431 in FIG. 7B; [0093]) to the encapsulation material (460) and to a first surface (upper plane) of each of the plurality of semiconductor dies (100a/200a/200b/100b);
forming a redistribution layer (441 in FIG. 9B; [0099]-[0100]) on a second surface (lower plane) of each of the plurality of semiconductor dies (100a/200a/200b/100b); and
removing (FIG. 8B; [0104]) a portion (at 450) of the encapsulation material (460) to expose a surface (lower plane) of the dieback conductive member (431).
Kim fails to disclose applying the encapsulation material (460) to the dieback conductive member (431) and the plurality of semiconductor dies (100a/200a/200b/
100b).
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to apply the encapsulation material (460) to the dieback conductive member (431) and the plurality of semiconductor dies (100a/200a/200b/100b) before applying the encapsulation material to the plurality of semiconductor dies (100a/200a/200b/100b), as disclosed by Kim, since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Re claim 18, Kim discloses the method of claim 16, wherein the dieback conductive member includes a plurality of conductive plates, each of the plurality of conductive plates coupled to a separate semiconductor die of the plurality of semiconductor dies (see claim 3).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Doan et al (US 2014/0087499 A1, hereafter Doan).
Re claim 19, Kim discloses the method of claim 18.
But, fails to disclose the method of further comprising: applying a metal layer to the first surface of each of a plurality of semiconductor dies (100a/200a/200b/100b); and
removing a portion of the metal layer between adjacent semiconductor dies (100a/200a/200b/100b) to form the plurality of conductive plates.
However,
Doan discloses in FIGS. 3-8 a method of forming conductive plates comprising applying a metal layer (as-deposited 70 in FIG. 8; [0056]) to the first surface (top plane) of each of a plurality of semiconductor dies (left/middle/right LEDs; [0056]); and removing a portion (by etching or lift-off; [0056]) of the metal layer (as-deposited 70) between adjacent semiconductor dies (left/middle/right LEDs) to form the plurality of conductive plates (electrodes/pads 70; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim by using the conductive plate forming method of Doan, by applying a metal layer to the first surface of each of a plurality of semiconductor dies (100a/200a/200b/100b); and removing a portion of the metal layer between adjacent semiconductor dies (100a/200a/200b/100b) to form the plurality of conductive plates, in a single parallel process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892