DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I, claims 1-9 and 17-20, in the reply filed on January 8, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Accordingly, claims 10-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 8, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 5, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, 8, 9, and 17-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsiao et al (US Pub 2025/0038074) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claim 1, Hsiao et al discloses a semiconductor device, comprising: a device layer (i.e. 102) having a frontside and a backside; a first interconnect structure (i.e. 110) disposed on the frontside of the device layer, and having a first seal ring structure (i.e. 150); a second interconnect structure (i.e. 112) disposed on the backside of the device layer; and a diode and a transistor (i.e. see at least paragraph 0023 disclosing the device layer includes at least diode and transistor) embedded in the device layer, wherein a gate of the transistor is electrically connected to the first seal ring structure by the diode (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figure 1).
In re claim 5, Hsiao et al discloses wherein the first interconnect structure (i.e. 110) includes: a first dielectric layer (i.e. 222) and a first conductive feature (i.e. 232, 236, 240) embedded in the first dielectric layer, and the diode is electrically connected to the first seal ring structure by a first portion of the first conductive feature (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figures 1 and 2).
In re claim 6, Hsiao et al discloses wherein the second interconnect structure (i.e. 112) includes: a second dielectric layer (i.e. 224) and a second conductive feature (i.e. 244) embedded in the second dielectric layer, and the second conductive feature is contact with the gate of the transistor (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figures 1 and 2).
In re claim 8, Hsiao et al discloses wherein: the first interconnect structure (i.e. 110) includes: a first dielectric layer (i.e. 222) and a first conductive feature (i.e. 232, 236, 240) embedded in the first dielectric layer; the second interconnect structure (i.e. 112) includes: a second dielectric layer (i.e. 224) and a second conductive feature (i.e. 244) embedded in the second dielectric layer, and the device layer (i.e. 102) further includes a conductive path (i.e. 212, 234) extending from the frontside of the device layer to the backside of the device layer (i.e. see at least Figure 2).
In re claim 9, Hsiao et al discloses wherein the second conductive feature is electrically connected to the first seal ring structure through the conductive path, a second portion of the first conductive feature, the gate of the transistor, the diode, and a first portion of the first conductive feature (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figures 1 and 2).
In re claim 17, Hsiao et al discloses a semiconductor device, comprising: a device layer (i.e. 102); a diode and a transistor embedded in the device layer (i.e. see at least paragraph 0023 disclosing the device layer includes at least diode and transistor), wherein a gate of the transistor is electrically connected to a charge pool (i.e. 150) by the diode (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figure 1), and the charge pool surrounds the transistor along a closed path from a plan view of the device layer (i.e. see at least Figure 3).
In re claim 18, Hsiao et al discloses further comprising: a first interconnect structure (i.e. 110) disposed on the frontside of the device layer, wherein the charge pool (i.e. 150) is embedded in the first interconnect structure (i.e. see at least Figure 1); and a second interconnect structure (i.e. 112) disposed on the backside of the device layer opposite to the frontside of the device.
In re claim 19, Hsiao et al discloses wherein the first interconnect structure (i.e. 110) includes: a first dielectric layer (i.e. 222) and a first conductive feature (i.e. 232, 236, 240) embedded in the first dielectric layer; the second interconnect structure (i.e. 112) includes: a second dielectric layer (i.e. 224) and a second conductive feature (i.e. 244) embedded in the second dielectric layer, and the device layer (i.e. 102) further includes a conductive path (i.e. 212, 234) extending from the frontside of the device layer to the backside of the device layer, the second conductive feature is electrically connected to the charge pool through the conductive path, a second portion of the first conductive feature, the gate of the transistor, the diode, and a first portion of the first conductive feature (i.e. it is inherent and well known in the art that device elements would all be connected together at least electrically; see at least Figures 1 and 2).
Allowable Subject Matter
Claims 2-4, 7, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Chen et al (US Pub 2023/0154870)
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/ANTHONY HO/Primary Examiner, Art Unit 2817