DETAILED ACTION
This Office action is in response to the election and amendment filed 24 February 2026. By this amendment, claim 2 is amended, claims 8-20 are cancelled; claims 21-33 are new. Claims 1-7 and 21-33 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I, claims 1-7 and newly added claims 21-33, in the reply filed on 24 February 2026 is acknowledged.
Claims 6, 26, and 29-33 are drawn to species non-elected; the claims to the different species recite the mutually exclusive characteristics of such species as set forth in the Restriction Requirement mailed 19 February 2026. Claims 6, 26, and 29-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 24 February 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 21-25, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0098588 A1 to Chung et al. (hereinafter “Chung”) in view of US 2022/0320088 A1 to Pan et al. (hereinafter “Pan”).
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Regarding independent claim 1, Chung (Figs. 19A-C; annotated Fig. 19B above) discloses a semiconductor structure comprising:
a semiconductor layer 210B (¶ 0019);
a first isolation feature 218 (Fig. 19B, left; ¶ 0025) and a second isolation feature 218 (Fig. 19B, right; ¶ 0025);
a first gate (Fig. 19B) includes:
a gate stack 268 (labelled in Fig. 17; ¶ 0038) that surrounds the semiconductor layer 210B, wherein the gate stack has a gate dielectric 264 (¶ 0038) and a gate electrode 266 (¶ 0038), the gate stack has a first sidewall (annotated Fig. 19B above) and a second sidewall (annotated Fig. 19B above), wherein the first sidewall is formed by the gate dielectric 264 and the gate electrode 266, and a gate endcap (annotated Fig. 19B above) disposed on the first sidewall (Examiner notes that the gate electrode and gate endcap of the claimed instant invention can be made of the same material [compare the materials listed in ¶ 0068 and ¶ 0074 of the instant specification] and thus would be indistinguishable as separate elements in the final device; the interpretation of the prior art is consistent with this observation);
a gate helmet 212 (¶ 0036) disposed over the gate stack, wherein a portion of the gate dielectric 264 is disposed between the gate electrode 266 and the gate helmet 212 (Figs. 19B, 19C).
Chung fails to expressly disclose: a first gate isolation wall and a second gate isolation wall, wherein the first gate isolation wall is disposed over the first isolation feature and the second gate isolation wall is disposed over the second isolation feature; the first gate disposed between the first gate isolation wall and the second gate isolation wall; and a gate contact disposed on the first gate, wherein the gate contact extends over the first gate isolation wall and connects the first gate to a second gate.
In the same field of endeavor, Pan (Fig. 27B) discloses a semiconductor structure including: a first gate isolation wall 264 (¶ 0063) and a second gate isolation wall 264, wherein the first gate isolation wall is disposed over a first isolation feature 250 (¶ 0024) and the second gate isolation wall 264 is disposed over a second isolation feature 250 (Fig. 27B); a first gate 370B (¶ 0056) disposed between the first gate isolation wall 264 and the second gate isolation wall 264 (Fig. 27B); and a gate contact 390/380B (¶¶ 0059-60) disposed on a first gate 370B (¶ 0056), wherein the gate contact extends over the first gate isolation wall 264 (Fig. 27B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chung to include first gate isolation wall and second gate isolation wall as taught by Pan for the purpose of reducing leakage paths between gates and source/drain contacts, thus improving device performance (Pan, ¶ 0032). It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chung to include a gate contact configuration as disclosed by Pan, and to provide a gate contact that connects the first gate to a second gate, for the purpose of providing necessary contacts for a functional device (Pan, ¶ 0060).
Regarding claim 2, the combination of Chung and Pan disclose the semiconductor structure of claim 1, wherein the gate contact 390/380B (Pan, Fig. 27B) extends over the first sidewall and physically contacts the gate endcap (Chung, annotated Fig. 19B above).
Regarding claim 3, Chung and Pan disclose the semiconductor structure of claim 1, Chung (Fig. 19B) discloses further wherein: the first sidewall (annotated Fig. 19B above) has a gate dielectric portion (portion of 264) disposed between a first gate electrode portion (portion of 266 between 210B/262/264 structures) and a second gate electrode portion (another portion of 266 between 210B/262/264 structures), the gate dielectric portion is formed by the gate dielectric 264, and the first gate electrode portion and the second gate electrode portion are each formed by the gate electrode 266; and the gate endcap (annotated Fig. 19B above) is disposed on the gate dielectric portion, the first gate electrode portion, and the second gate electrode portion, wherein the gate endcap connects the first gate electrode portion and the second gate electrode portion (Fig. 19B).
Regarding claim 4, Chung and Pan disclose the semiconductor structure of claim 1, Chung (Fig. 19B) discloses further wherein: the first sidewall (annotated Fig. 19B above) has a gate dielectric portion (portion of 264) disposed between a first gate electrode portion (portion of 266 between 210B/262/264 structures) and a second gate electrode portion (another portion of 266 between 210B/262/264 structures), the gate dielectric portion is formed by the gate dielectric 264, and the first gate electrode portion and the second gate electrode portion are each formed by the gate electrode 266; and the gate endcap (annotated Fig. 19B above) has a first gate endcap segment (segment of “gate endcap” on portion of 266 between 210B/262/264) disposed on the first gate electrode portion and a second gate endcap segment (segment of “gate endcap” on portion of 266 between 210B/262/264) disposed on the second gate electrode portion (annotated Fig. 19B above).
Regarding claim 5, Chung and Pan disclose the semiconductor structure of claim 4, Chung (Fig. 19B) discloses further wherein the first gate endcap segment and the second gate endcap segment extend over the gate dielectric portion (“first gate endcap segment” and “second gate endcap segment“ can be defined to be consistent with the above limitations).
Regarding claim 7, Chung and Pan disclose the semiconductor structure of claim 1, wherein the gate endcap provides the first gate with a gate sidewall (Chung, annotated Fig. 19B above), however fails to expressly disclose having a scalloped profile.
Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975). Here, the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to the claimed scalloped profile, thus for this reason and in view of the disclosures of Chung and Pan, the recited particular shape is deemed to have been a design consideration within the skill of the art.
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Regarding independent claim 21, Chung (Figs. 19A-C - figures are understood to illustrate a representative structure of many disposed on the substrate, as is customary in the art) discloses a semiconductor structure comprising:
a first gate stack disposed on a first semiconductor layer 210B (¶ 0019), wherein the first gate stack has a first gate dielectric 264 (¶ 0038) and a first gate electrode 266 (¶ 0038) and first sidewalls (labelled in annotated Fig. 19B above) of the first gate stack are formed by both the first gate dielectric 264 and the first gate electrode 266 (Examiner notes that the gate electrode and gate endcap of the claimed instant invention can be made of the same material [compare the materials listed in ¶ 0068 and ¶ 0074 of the instant specification] and thus would be indistinguishable as separate elements in the final device; the interpretation of the prior art is consistent with this observation);
a second gate stack (having the same structure as in Figs 19A-C) disposed on a second semiconductor layer 210B, wherein the second gate stack has a second gate dielectric 264 and a second gate electrode 266 and second sidewalls (see Fig. 19B above) of the second gate stack are formed by both the second gate dielectric 264 and the second gate electrode 266 (Examiner notes that the gate electrode and gate endcap [as recited in claim 22] of the claimed instant invention can be made of the same material [compare the materials listed in ¶ 0068 and ¶ 0074 of the instant specification] and thus would be indistinguishable as separate elements in the final device; the interpretation of the prior art is consistent with this observation);
a first gate helmet 212 (¶ 0036) and a second gate helmet 212, wherein the first gate helmet is disposed on the first gate stack and the second gate helmet is disposed on the second gate stack (Figs. 19B-C).
Chung fails to expressly disclose: a gate isolation wall disposed between the first gate stack and the second gate stack; and a gate contact disposed on the first gate stack and the second gate stack, wherein the gate contact is further disposed on the gate isolation wall and the gate contact is disposed between the first gate helmet and the second gate helmet. In the same field of endeavor, Pan (Fig. 27B) discloses a semiconductor structure including: a gate isolation wall 264 (¶ 0063) disposed between a first gate stack 370B (¶ 0056) and second gate stack 370A (¶ 0056), and a gate contact 390/380B (¶¶ 0059-60) disposed on the first gate stack 370B and the second gate stack 370A, wherein the gate contact is further disposed on the gate isolation wall 264 (Fig. 27B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chung to include a gate isolation wall disposed between the first gate stack and second gate stack as taught by Pan for the purpose of reducing leakage paths between gates and source/drain contacts, thus improving device performance (Pan, ¶ 0032). It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chung to include a gate contact configuration as disclosed by Pan, and to dispose the gate contact between the first gate helmet and the second gate helmet, for the purpose of providing necessary contacts for a functional device (Pan, ¶ 0060).
Regarding claim 22, Chung and Pan disclose the semiconductor structure of claim 21, Chung (Fig. 19B) discloses further comprising: a first gate endcap (annotated Fig. 19B above) disposed on a first one of the first sidewalls of the first gate stack, wherein the first gate endcap connects a first portion (portion of 266 between 210B/262/264 structures) of the first gate electrode and a second portion (another portion of 266 between 210B/262/264 structures) of the first gate electrode; and a second gate endcap (annotated Fig. 19B above, on the second gate stack having the same structure as that of Fig. 19) disposed on a first one of the second sidewalls of the second gate stack, wherein the second gate endcap connects a first portion (portion of 266 between 210B/262/264 structures) of the second gate electrode and a second portion (another portion of 266 between 210B/262/264 structures) of the second gate electrode (Chung, Fig. 19B).
Regarding claim 23, Chung and Pan disclose the semiconductor structure of claim 22, Chung (Fig. 19A-C) wherein the first gate endcap (annotated Fig. 19B above) extends above the first gate electrode (gate endcap extends above top 210B covered on top and bottom by portions of 266, and along 212) and the second gate endcap (annotated Fig. 19B above) extends above the second gate electrode (gate endcap extends above top 210B covered on top and bottom by portions of 266, and along 212).
Regarding claim 24, Chung and Pan disclose the semiconductor structure of claim 22, wherein Chung (Fig. 19B) discloses further: the first gate endcap (annotated Fig. 19B above) extends over the first gate helmet 212 and the second gate endcap (annotated Fig. 19B above) extends over the second gate helmet 212.
Regarding claim 25, Chung and Pan disclose the semiconductor structure of claim 22, however fail to expressly disclose: wherein each of the first gate endcap and the second gate endcap includes a surface having a wavy profile.
Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975). Here, the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to the claimed wavy profile, thus for this reason and in view of the disclosures of Chung and Pan, the recited particular shape is deemed to have been a design consideration within the skill of the art.
Regarding claim 27, Chung and Pan disclose the semiconductor structure of claim 22, the combination discloses further comprising: a third gate endcap (annotated Fig. 19B above) and a fourth gate endcap (annotated Fig. 19B above), wherein the third gate endcap is disposed on a second one (annotated Fig. 19B - right sidewall) of the first sidewalls of the first gate stack (Fig. 19B) and the fourth gate endcap is disposed on a second one (annotated Fig. 19B - left sidewall) of the second sidewalls of the second gate stack (same structure of Fig. 19B, located to the right side of the first gate stack); wherein the gate isolation wall 264 (Pan, Fig. 27B) is disposed between the third gate endcap and the fourth gate endcap; and wherein the gate contact 390/380B (Pan, Fig. 27B) is disposed on the third gate endcap and the fourth gate endcap (Chung, Fig. 19B).
Regarding claim 28, Chung and Pan disclose the semiconductor structure of claim 27, Chung discloses further: wherein the third gate endcap (annotated Fig. 19B) connects the first portion (portion of 266 between 210B/262/264 structures) of the first gate electrode and the second portion (another portion of 266 between 210B/262/264 structures) of the first gate electrode (annotated Fig. 19B above) and the fourth gate endcap (annotated Fig. 19B) connects the first portion (portion of 266 between 210B/262/264 structures) of the second gate electrode and the second portion (another portion of 266 between 210B/262/264 structures) of the second gate electrode (annotated Fig. 19B above).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2023/0402536 A1 to Chiang et al. disclosing a gate-all-around semiconductor structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
31 March 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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