DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 10 December 2024. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the S/D contact” at line 3 which makes unclear which S/D contact is being referenced. Claim 1 requires a first S/D contact and a second S/D contact and then the initial portion of claim 4 also recites an S/D contact. Claims 5-7 include and do not cure the deficiencies of claim 4.
Claim 5 recites “the S/D contact” at line 6 which makes unclear which S/D contact is being referenced. Claim 1 requires a first S/D contact and a second S/D contact and then the initial portion of claim 4 also recites an S/D contact. Claims 6 and 7 include and do not cure the deficiencies of claim 5.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8, 10, 11, 17 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (U.S. Patent Application Publication 2025/0048686).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to Claim 1, Wang teaches, in Fig. 4A and 4B, semiconductor device, comprising: a semiconductor substrate (56); a transistor formed over the semiconductor substrate (56), wherein the transistor includes a first source/drain (S/D) feature (70), a second S/D feature (70), a channel region (78) interposed between the first and second S/D features (70), and a gate stack (60) engaging the channel region (78); a first S/D contact (72) landing on a top surface of the first S/D feature (70); a second S/D contact (72) landing on a top surface of the second S/D feature (70); and a dielectric plug (88; backside dielectric vias; par. 22, 32-33 and 46) penetrating [entirely] through the semiconductor substrate (56) and landing on a bottom surface of the first S/D feature (70), the dielectric plug (88) spans a width equal to or smaller than a width of the first S/D feature (70). It is also noted that Wang teaches a dielectric plug (68; dielectric feature; par. 24-25 and 31) penetrating [partially] through the semiconductor substrate (56) and landing on a bottom surface of the first S/D feature (70), the dielectric plug (68) spans a width equal to or smaller than a width of the first S/D feature (70).
Referring to Claim 2, Wang further teaches wherein the dielectric plug (88 or 68) is a first dielectric plug, further comprising: a second dielectric plug (68 or 88) [entirely or partially] penetrating through the semiconductor substrate (56) and landing on a bottom surface of the second S/D feature (70), wherein the second dielectric plug is separated from the first dielectric plug by a portion of the semiconductor substrate (56). Wang teaches:
[0032] As noted above, the backside vias 64 may have some alternative structure described in FIGS. 4A and 4B. FIG. 4A illustrates a top view of the IC structure 50 while FIG. 4B illustrates a sectional view of the IC structure 50 along the dashed line BB′, constructed according to some embodiments. The IC structure 50 illustrated in FIGS. 4A and 4B is similar to the IC structure 50 illustrated in FIGS. 3A-3B. However, some backside vias 64 are replaced with backside dielectric vias 88. The backside dielectric vias 88 are dielectric features and are configured for isolation with enhance isolation effectiveness. Therefore, the semiconductor islands of the semiconductor substrate 56 are separated and isolated from each other by the backside dielectric vias 88. For clarity, the backside vias 64 are also referred to as backside conductive vias 64.
[0033] In FIG. 4A, the device structure includes active regions oriented along X direction and gates oriented along Y direction. Furthermore, the backside dielectric layer 82, the dielectric feature 68, the dielectric barrier layer 66, and the backside dielectric vias 88 are configured to collectively isolate one semiconductor island from adjacent semiconductor islands. In some embodiments, the device structure includes dielectric gate, dielectric gate-cut feature or both to provide additional isolation effect to the semiconductor islands and the FETs formed thereon.
It is noted that Wang teaches a plurality of dielectric plugs (88) and a plurality of dielectric plugs (68).
As insofar as Claim 4 is definite, Wang further teaches an [third] S/D contact (64) penetrating through the semiconductor substrate (56) and landing on a bottom surface of the second S/D feature (70), wherein the [third] S/D contact (64) is separated from the dielectric plug (88 or 68) by a portion of the semiconductor substrate (56).
Referring to Claim 8, Wang further teaches wherein a top surface of the dielectric plug (68) is above the bottom surface of the gate stack (60) as shown in Fig. 3D for example (par. 25).
Referring to Claim 10, Wang teaches in Fig. 4A and 4B, a semiconductor device, comprising: a semiconductor substrate (56); transistors formed over the semiconductor substrate, wherein each of the transistors includes a channel region (78) interposed between source/drain (S/D) features (70) and a gate stack (60) engaging the channel region (78); S/D contacts (72) landing on top surfaces of the S/D features (70); and dielectric plugs (88; backside dielectric vias; par. 22, 32-33 and 46) penetrating through the semiconductor substrate (56) and landing on bottom surfaces of the S/D features (70).
Referring to Claim 11, Wang further teaches wherein one of the dielectric plugs (88) is a first dielectric plug landing on the bottom surface of a first S/D feature (70), another one of the dielectric plugs (88) is a second dielectric plug landing on the bottom surface of a second S/D feature (70), and the first and the second dielectric plugs are embedded in and separated from each other by the semiconductor substrate (56).
Referring to Claim 17, Wang teaches a method of forming a semiconductor device, comprising: receiving a workpiece having transistors formed over a substrate (56), each of the transistors includes a channel region (78) interposed between source/drain (S/D) features (70), and a gate stack (60) engaging the channel region (78); thinning down the substrate (56) from a backside of the workpiece (par. 20, 27, 56; claims 10 and 11); and forming dielectric plugs (88) penetrating through the thinned down substrate (56) to land on a first and a second S/D feature (70) of the transistors, wherein the dielectric plugs (88) are separated from each other by the thinned down substrate (56).
Referring to Claim 18, Wang further teaches etching through the thinned down substrate (56) to form a contact trench that expose a third S/D feature (70) of the transistors; and forming a contact (64) in the contact trench (par. 22).
Allowable Subject Matter
Claims 3, 5-7, 9, 12-16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first dielectric plug further includes a first dielectric fill layer surrounded by a first barrier layer, the first dielectric fill layer has a first dielectric material, the first barrier layer has a second dielectric material different from the first dielectric material, and the first barrier layer directly contacts the bottom surface of the first S/D feature, wherein the second dielectric plug further includes a second dielectric fill layer surrounded by a second barrier layer, the second dielectric fill layer has the first dielectric material, the second barrier layer has the second dielectric material, and the second barrier layer directly contacts the bottom surface of the second S/D feature in combination with all of the limitations of claims 1-3.
Regarding Claim 5, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the dielectric plug further includes a dielectric fill layer surrounded by a first barrier layer, the dielectric fill layer has a first dielectric material, the first barrier layer has a second dielectric material different from the first dielectric material, and the first barrier layer directly contacts the bottom surface of the first S/D feature, wherein the S/D contact further includes a conductive fill layer surrounded by a second barrier layer, the second barrier layer has the second dielectric material, and the conductive fill layer directly contacts the bottom surface of the second S/D feature in combination with all of the limitations of claims 1, 4 and 5. Claims 6 and 7 include the limitations of claim 5.
Regarding Claim 9, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device a vertical distance between the top surface of the dielectric plug and the bottom surface of the gate stack is greater than 5 nm in combination with all of the limitations of claim 1, 8 and 9.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein each of the dielectric plugs spans laterally between two adjacent channel regions in combination with all of the limitations of claims 10 and 12. Claims 13 and 14 include the limitations of claim 12.
Regarding Claim 15, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein one of the dielectric plugs has a bulk portion and multiple penetrating portions protruding from the bulk portion, the bulk portion penetrates through the semiconductor substrate to a first depth, and the penetrating portions penetrates through the semiconductor substrate to a second depth greater than the first depth, wherein the penetrating portions directly land on the bottom surfaces of the S/D features in combination with all of the limitations of claims 10 and 15. Claim 16 includes the limitations of claim 15.
Regarding Claim 19, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method wherein the forming of the dielectric plugs includes forming a dummy dielectric plug penetrating through the thinned down contact to land on a third S/D feature of the transistors, further comprising: removing the dummy dielectric plug to form a contact trench; and forming a contact in the contact trench in combination with all of the limitations of claims 17 and 19.
Regarding Claim 20, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method wherein the forming of the dielectric plugs comprises: etching the thinned down substrate to form first trenches that expose the S/D features, wherein the etching includes recessing a portion of the S/D features; and depositing a dielectric material in the first trenches in combination with all of the limitations of claims 17 and 20.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896