DETAILED ACTION
Election/Restrictions
Applicant elected invention Group I and Species III (FIGs. 13A-13B) in the reply filed on 1/29/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 22-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 22 reciting “the first dielectric material has a higher Young's modulus than the second dielectric material” and claim 23 reciting “the first dielectric material has a higher glass transition temperature than the second dielectric material” lacks adequate written description. Applicant’s original disclosure describes the second dielectric material of the dielectric structure around the vias as having higher Young’s modulus and higher glass transition temperature. There is no explicit support for the first dielectric material of the dielectric layers to have higher Young’s modulus and higher glass transition temperature.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6, 13, and 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5 reciting “a first coefficient of thermal expansion (CTE) of the first dielectric material is substantially the same as a second CTE of the second dielectric material” renders the claim indefinite. It is unclear what constitutes “substantially the same”. There is no clear guidance on what is intended to be included or excluded by “substantially the same”. Thus, the intended scope of the claim is rendered indefinite.
Claim 13 reciting “a second coefficient of thermal expansion (CTE) of the second dielectric material is substantially the same as a first CTE of the first dielectric material” renders the claim indefinite for similar reason as claim 5.
Claim 22 reciting “the first dielectric material has a higher Young's modulus than the second dielectric material” and claim 23 reciting “the first dielectric material has a higher glass transition temperature than the second dielectric material” renders the claim indefinite. Such relationship is not consistent with the disclosure as detailed above. It is unclear what is intended by the “first dielectric material” and the “second dielectric material” in these claims.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 11-13, 21-23, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. US 2003/0116854 A1 (Ito).
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In re claim 1, Ito discloses (e.g. FIGs. 5-14) a semiconductor package comprising:
a die 24 having a conductive pad 12,42 at a first (top) side of the die; and
a redistribution structure (structure above 24) over the first (top) side of the die and electrically coupled to the die, comprising:
a first dielectric layer 14,44,52 comprising a first dielectric material;
a first via 19a,49a in the first dielectric layer 14,44,52, wherein the first via 19a,49a is electrically coupled to the conductive pad 12 of the die; and
a first dielectric structure 16,26,48,54 embedded in the first dielectric layer 14,44,52, wherein the first dielectric structure 16,26,48,54 comprises a second dielectric material different from the first dielectric material 14,44,52 (¶ 50,89,93,109), wherein the first dielectric structure 16,26,48,54 laterally surrounds the first via 19a,49a and contacts sidewalls of the first via 19a,49a (including barrier 18).
In re claim 2, Ito discloses wherein a second Young's modulus of the second dielectric material 16,26,48,54 (high Young’s modulus insulation film, ¶ 50,89,93,109) is higher than a first Young's modulus of the first dielectric material 14,44,52 (¶ 48).
In re claim 3, Ito discloses wherein a second glass transition temperature of the second dielectric material 16,26,48,54 (e.g. SiCN, ¶ 50) is higher than a first glass transition temperature of the first dielectric material 14,44,52 (e.g. SiO(CH3)x, ¶ 48) .
In re claim 4, Ito discloses (e.g. FIG. 14) wherein the first dielectric material 52 is a first photosensitive polymer material (¶ 109, no specific “photosensitive polymer material” claimed would distinguish over the polymer material taught by Ito), and the second dielectric material is a second photosensitive polymer material (the second dielectric material includes a base polymer material and aluminum carbide 54 formed by reacting a portion of the base polymer, as such that an immediate portion of the polymer material is considered to be a part of the second dielectric material forming the dielectric structure surrounding the via).
In re claim 5, as best understood, Ito discloses (e.g. FIGs. 10 & 14) wherein a first coefficient of thermal expansion (CTE) of the first dielectric material 14,44,52 is substantially the same as a second CTE of the second dielectric material (the second dielectric material includes a base polymer material and aluminum containing layer 48,54 formed by reacting a portion of the base polymer, as such that an immediate portion of the polymer material is considered to be a part of the second dielectric material forming the dielectric structure surrounding the via which has a CTE that is the same as the portion of polymer further distant from the via).
In re claim 6, Ito discloses (e.g. FIGs. 9, 10, 12 & 14) wherein an upper surface of the first dielectric layer 14,44,52 distal from the die 24 is level with an upper surface of the first dielectric structure 26,48,54, distal from the die 24, wherein a lower surface of the first dielectric layer 14,44,52 facing the die 24 is level with a lower surface of the first dielectric structure 26, 48, 54 facing the die 24.
In re claim 7, Ito discloses (e.g. FIGs. 10-14) wherein the redistribution structure further comprises:
a second dielectric layer 46,53 comprising the first dielectric material (¶ 92,109), wherein the first dielectric layer 44,52 is between the second dielectric layer 46,53 and the die 24;
a second via 49b in the second dielectric layer 46,53, wherein the second via 49b is electrically coupled to the first via 49a, wherein a first center axis of the first via 49a is aligned with a second center axis of the second via 49b along a same line; and
a second dielectric structure 48,54 embedded in the second dielectric layer 46,53, wherein the second dielectric structure 48,54 comprises the second dielectric material (¶ 93,109), wherein the second dielectric structure 48,54 surrounds the second via 49b and contacts sidewalls of the second via 49b.
In re claim 11, Ito discloses (e.g. FIGs. 5-14) a semiconductor package comprising:
a die 24 (see FIG. 5) having a conductive pad 12,42 at a first (top) side of the die; and
a redistribution structure (structure above 24) over the first (top) side of the die 24 and electrically coupled to the die, comprising:
a first dielectric layer 44,52 (or lower portion of 14) comprising a first dielectric material;
a second dielectric layer 46,53 (or upper portion of 14) comprising the first dielectric material (¶ 48,92,109), wherein the first dielectric layer 44,52 (or lower 14) is between the second dielectric layer 46,53 (or upper 14) and the die 24;
a first via 19a,49a in the first dielectric layer 44,52 (or lower 14) and electrically coupled to the conductive pad 12,42 of the die;
a second via 19b,49b in the second dielectric layer 46,53 (or upper 14) and electrically coupled to the first via 19a,49a, wherein a first center axis of the first via 19a,49a and a second center axis of the second via 19b,49b are aligned along a same line;
a first dielectric structure 16,26,48,54 embedded in the first dielectric layer 44,52 (or lower 14) and around the first via 19a,49a, wherein the first dielectric structure 16,26,48,54 comprises a second dielectric material different from the first dielectric material 14,44,52 (¶ 50,89,93,109), wherein the first dielectric structure 16,2648,54 contacts sidewalls of the first via 19a,49a (including barrier 18); and
a second dielectric structure 16,26,48,54 embedded in the second dielectric layer 46,53 (or upper 14) and around the second via 19b,49b, wherein the second dielectric structure 16,26,48,54 comprises the second dielectric material and contacts sidewalls of the second via 19b,49b (including barrier 18).
In re claim 12, Ito discloses wherein the second dielectric material 16,26,48,54 has a higher Young's modulus than the first dielectric material 14,44,52 (¶ 48,50,89,93,109), wherein the second dielectric material 16,26,48,54 (e.g. SiCN, ¶ 50) has a higher glass transition temperature than the first dielectric material 14,44,52 (e.g. SiO(CH3)x, ¶ 48) .
In re claim 13, as best understood, Ito discloses (e.g. FIGs. 10 & 14) wherein a second coefficient of thermal expansion (CTE) of the second dielectric material 14,44,52 is substantially the same as a first CTE of the first dielectric material (the second dielectric material includes a base polymer material and aluminum containing layer 48,54 formed by reacting a portion of the base polymer, as such that an immediate portion of the polymer material is considered to be a part of the second dielectric material forming the dielectric structure surrounding the via which has a CTE that is the same as the portion of polymer further distant from the via).
In re claim 21, Ito discloses (e.g. FIGs. 10-14) a semiconductor package comprising:
a die 30 (including underlying substrate) embedded in a molding material (no specific “molding material” claimed to distinguish over the insulating layer below 11 covering the active element 30, see FIG. 5); and
a redistribution structure (structure above 24) over the die and the molding material, comprising:
a first via 49a over and electrically coupled to a die connector 42 of the die;
a first dielectric structure 48,54 around the first via 49a;
a first dielectric layer 44,52 around the first dielectric structure 48,54, wherein the first dielectric layer 44,52 comprises a first dielectric material, and the first dielectric structure 48,54 comprises a second dielectric material different from the first dielectric material (¶ 93,109), wherein an upper surface of the first dielectric structure 48,54 distal from the die is level with an upper surface of the first dielectric layer 44,52;
a second via 49b over and electrically coupled to the first via 49a, wherein a first center axis of the first via 49a and a second center axis of the second via 49b are aligned along a same line;
a second dielectric structure 48,54 around the second via 49b, wherein the second dielectric structure 48,54 comprises the second dielectric material (¶ 93,109);
a second dielectric layer 46+47,53+47 around the second dielectric structure 48,54, wherein the second dielectric layer 46+47,53+47 comprises the first dielectric material (¶ 92,109), wherein an upper surface of the second dielectric structure 48,54 distal from the die is level with an upper surface of the second dielectric layer 46+47,53+47.
In re claim 22, as best understood, Ito discloses wherein the second dielectric material 48,54 (high Young’s modulus insulation film, ¶ 50,89,93,109) has a higher Young's modulus than the first dielectric material 14,44,52 (¶ 48).
In re claim 23, as best understood, Ito discloses wherein the second dielectric material 16,26,48,54 (e.g. SiCN, ¶ 50; or alumina, ¶ 93) has a higher glass transition temperature than the first dielectric material 14,44,52 (e.g. SiO(CH3)x, ¶ 48; or porous organosilicon oxide, ¶ 92; or aromatic hydrocarbon, ¶ 109).
In re claim 25, Ito discloses (e.g. FIGs. 10-14) wherein a sidewall of the molding material (sidewall of 24 as shown in FIG. 10-14 including a “molding layer” below 11 covering the active element 30, see FIG. 5) is aligned along a same line with a first sidewall of the first dielectric layer 44,52 and a second sidewall of the second dielectric layer 46,53.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10, 14-15, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claims 1, 11, and 21 above, and further in view of Wang et al. US 2017/0047297 A1 (Wang).
In re claim 8, Ito discloses the claimed redistribution structure over the die including showing specifically one level wiring 19,49. Ito does not explicitly discloses the redistribution structure further comprises:
a third dielectric layer comprising the first dielectric material, wherein the third dielectric layer is between the first dielectric layer and the die; and
a third via in the third dielectric layer, wherein the third via is electrically coupled to the first via, wherein the third dielectric layer surrounds and contacts sidewalls of the third via.
However, Wang discloses (e.g. FIG. 17) a semiconductor package comprising a redistribution structure over a die including multiple wiring levels each including vias 28,50,66 surrounded by dielectric layers. The multilevel interconnect structures provides various electrical routings need of the device.
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Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the wiring structure of Ito to form multiple interconnection levels to facilitate electrical routings as is well-known in the art. As such, it would be obvious to obtain a structure as depicted below showing repetition of the wiring layers.
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As such, Ito as modified in view of Wang teaches the redistribution structure further comprises:
a third dielectric layer 52+54 comprising the first dielectric material 52, wherein the third dielectric layer 52+54 is between the first dielectric layer 52 (around first via) and the die 24; and
a third via in the third dielectric layer 52+54, wherein the third via is electrically coupled to the first via, wherein the third dielectric layer 52+54 surrounds and contacts sidewalls of the third via 49a (third via).
In re claim 9, Wang discloses (e.g. FIG. 17) third vias 28 in the lower interconnect level, wherein a third center axis of the third via 28 is spaced apart from the first center axis of the first via 50, wherein the redistribution structure further comprises a conductive line 26 connecting the first via 50 and the third via 28.
In re claim 10, Ito as modified in view of Wang (see FIG. 14 annotated above) teaches a third center axis of the third via (a lower via 49a) is aligned with the first center axis of the first via (an upper via 49a) along the same line.
Claim 14 recites limitation mirroring claim 8 and is obvious in view of Ito and Wang as detailed in the rejection of claim 8 above.
In re claim 15, Wang discloses (e.g. FIG. 17) a third via 28 in the lower interconnect level, wherein a third center axis of the third via 28 is spaced apart from the first center axis of the first via 50.
In re claim 24, Ito discloses the claimed redistribution structure over the die including showing specifically one level wiring 19,49. Ito does not explicitly discloses the redistribution structure further comprises:
a third via under the first via and electrically coupled to the die connector of the first die, wherein a third center axis of the third via is laterally spaced apart from the first center axis of the first via;
a third dielectric layer around and contacting sidewalls of the third via, wherein the third dielectric layer comprises the first dielectric material; and
a conductive line along an upper surface of the third dielectric layer distal from the die, wherein the conductive line electrically couples the third via with the first via.
However, Wang discloses (e.g. FIG. 17) a semiconductor package comprising a redistribution structure over a die including multiple wiring levels each including vias 28,50,66 surrounded by dielectric layers, including
a third via 28 under the first via 50 and electrically coupled to the die connector (e.g. lower level wiring 26) of the first die, wherein a third center axis of the third via 28 (middle level via 28 shown in FIG. 17) is laterally spaced apart from the first center axis of the first via 50;
a third dielectric layer 25 around and contacting sidewalls of the third via 28, wherein the third dielectric layer 25 comprises the first dielectric material (other dielectric layer 25); and
a conductive line 26 along an upper surface of the third dielectric layer 25 distal from the die, wherein the conductive line 26 electrically couples the third via 28 with the first via 50 (or other 28).
The multilevel interconnect structures provides various electrical routings need of the device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide additional wiring levels to form multiple interconnection levels as taught by Wang to facilitate electrical routings as is well-known in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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