Prosecution Insights
Last updated: July 05, 2026
Application No. 18/482,190

STACKED MULTI-GATE DEVICE WITH FRONT-AND-BACK INTERCONNECTION AND METHODS FOR FORMING THE SAME

Non-Final OA §112
Filed
Oct 06, 2023
Examiner
HALL, VICTORIA KATHLEEN
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
693 granted / 827 resolved
+15.8% vs TC avg
Strong +19% interview lift
Without
With
+18.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
37 currently pending
Career history
854
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
64.4%
+24.4% vs TC avg
§102
4.6%
-35.4% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 827 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions After the Office issued a restriction requirement on December 18, 2025, applicants responded February 10, 2026, canceling claims 13-20, adding new claims 21-28, and withdrawing claim 11 from consideration. Applicant’s election without traverse of claims 1-10 and 12 in the reply filed on February 10, 2026 is acknowledged. Drawings The drawings are objected to because of the following informalities: In Figure 3, delete the reference to source/drain recesses 46 in the figure. The source/drain recesses are discussed in Figure 4. PNG media_image1.png 499 519 media_image1.png Greyscale In Figure 19, check whether reference number 80 should be 82B. PNG media_image2.png 314 649 media_image2.png Greyscale In Figures 24 and 25, change the reference in the upper right corner from the lower transistor to the upper transistor, which is the subject of these drawings. Specifically, change 86L to 86U and change 90L to 90U. PNG media_image3.png 702 761 media_image3.png Greyscale In Figure 41, (1) in step 210, change “Recessing” to “recessing”, and (2) in step 228, change “single diffusion break” to “CESL”. See applicants’ specification, page 13, paragraph 46. PNG media_image4.png 472 1130 media_image4.png Greyscale Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Applicants’ amendments, filed September 13, 2025, add no new matter and are accepted and entered. The Office noted the use of the term COPDE on page 16, paragraph 59, which did not have a definition. However, after searching the prior art, the Office identified a reference to COPDE, defining the term as relating to lithography/etch/thin film deposition. See Chiu, U.S. Pat. Pub. No. 2025/0159967, paragraph 10. No objection is made. The Office is noting this for the record. The abstract of the disclosure is objected to because the abstract exceeds the 150 word limit. The current word count is 152 words (counting hyphenated words as one word). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). The disclosure is objected to because of the following informalities: Page 29, paragraph 104, last line of the paragraph: Should 26U be 26L? the lower device is discussed in this section. Appropriate correction is required. Claim Objections Claim 22 is objected to because of the following informalities: Claim 22, line 4: After “each” add “semiconductor layer”. Claim 22, line 5: After “and”, add “each inner spacer of”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 7, which depends from claim 6, which depends from claim 1: Claim 1 requires the following: performing a first etching process to form a first opening, wherein the first etching process comprises: etching a gate stack between the first CFET and the second CFET; and etching a plurality of alternating structures vertically aligned to the gate stack; filling the first opening with a dielectric material to form a dielectric region; performing a second etching process to etch a middle portion of the dielectric region and to form a second opening; and filling the second opening with a conductive material to form a through-via. (emphasis added). Claim 6 requires the following: wherein the first etching process comprises: a third etching process performed from a front side of a respective wafer comprising the first CFET and the second CFET; and a fourth etching process performed from a backside of the respective wafer. (emphasis added). This language ties the third and fourth etching processes to the first etching process which etches the first opening in a gate stack and plurality of alternating structures between the first and second CFETs. Claim 7 requires the following: after the third etching process and before the fourth etching process, filling a first portion of the second opening formed by the third etching process with a first part of the conductive material; and after the fourth etching process, filling a second portion of the second opening formed by the fourth etching process with a second part of the conductive material. (emphasis added). The language referring to the second opening being formed by the third etching process conflicts with claim 1’s requirement that the second opening be formed by the second etching process. Furthermore, the language referring to the second opening formed by the fourth etching process conflicts with claim 1’s requirement that the second opening be formed by the second etching process. Because claim 7’s requirements conflict with claim 1, claim 7 is rejected as indefinite. Remarks Although claim 11 is withdrawn, the Office reviewed claim 11 for any informalities or Section 112(b) issues. None were found. Claim 11 is expected to be re-joined. Allowable Subject Matter Claims 1-6, 8-10, 12, 21, and 23-28 are allowed, with claim 22 being allowable once the informalities were addressed. Claim 7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “performing a first etching process to form a first opening, wherein the first etching process comprises: etching a gate stack between the first CFET and the second CFET; and etching a plurality of alternating structures vertically aligned to the gate stack; filling the first opening with a dielectric material to form a dielectric region; performing a second etching process to etch a middle portion of the dielectric region and to form a second opening; and filling the second opening with a conductive material to form a through-via”, in combination with the remaining limitations of the claim. With regard to claims 2-10 and 12: The claims have been found allowable due to their dependency from claim 1 above. With regard to claim 21: The claim has been found allowable because the prior art of record does not disclose “forming a dielectric region in middle between the first CFET and the second CFET; etching the dielectric region to form a dielectric liner that comprises: an upper portion between the first upper transistor and the second upper transistor; and a lower portion between the first lower transistor and the second lower transistor; forming a through-via encircled by the dielectric liner; forming a first contact plug overlying and connecting to the through-via; and forming a second contact plug underlying and connecting to the through-via”, in combination with the remaining limitations of the claim. With regard to claims 22-25: The claims have been found allowable due to their dependency from claim 21 above. With regard to claim 26: The claim has been found allowable because the prior art of record does not disclose “forming a dielectric liner comprising: an upper portion contacting a first sidewall of the second gate spacer; and a lower portion contacting a second sidewall of the first gate spacer, wherein the dielectric liner encircles an opening; and filling the opening with a conductive material to form a through-via”, in combination with the remaining limitations of the claim. With regard to claims 27 and 28: The claims have been found allowable due to their dependency from claim 26 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Victoria K. Hall/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Oct 06, 2023
Application Filed
Sep 13, 2025
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME
3y 8m to grant Granted Jun 23, 2026
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DISPLAY PANEL
3y 5m to grant Granted Jun 02, 2026
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3y 2m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+18.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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