Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of Species I, claims 1-20, in the “Response to Restriction Requirement” filed on 07/20/2026 is acknowledged and entered by the Examiner. As claims 11-20 have been previously cancelled by the Applicant, the Examiner will examine claim 1-10.
This office action consider claims 1-10 and 21-30 pending for prosecution, wherein non-elected claims 21-30 are withdrawn from further consideration, and claims 1-10 are presented for examination (as claims 11-20 have been previously cancelled).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1, 4, 7, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20210005527 A1; hereinafter Choi).
Regarding claim 1, Choi teaches a method (see the entire document, specifically Fig. 1+; [0002+], and as cited below), comprising (see alternative rejection for claim 1 below):
forming a first device die (see Fig. 1; [0019-0040]) comprising:
forming integrated circuits on a first semiconductor substrate (200b; Fig. 1; [0015, 0025-0028]); and
forming a thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]) extending into the first semiconductor substrate (200b; Fig. 1; [0015, 0025-0028]); and
attaching a cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]) over and contacting the first semiconductor substrate (200b; Fig. 1; [0015, 0025-0028]) to form a package, wherein the cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]) is thermally coupled to the thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]).
Regarding claim 4, Choi teaches all of the features of claim 1.
Choi further teaches wherein the thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]) penetrates through the first semiconductor substrate (200b; Fig. 1; [0015, 0025-0028]), and the thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]) is in physical contact with the cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]).
Regarding claim 7, Choi teaches all of the features of claim 1.
Choi further teaches wherein the thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]) is electrically floating.
Regarding claim 8, Choi teaches all of the features of claim 1.
Choi further comprising bonding a second device die (200a; Fig. 1; [0015, 0025-0028]) to the first device die (200b; Fig. 1; [0015, 0025-0028]), with the second device (200a; Fig. 1; [0015, 0025-0028]) die being an additional part of the package, wherein the second device die (200a; Fig. 1; [0015, 0025-0028]) comprises: a second semiconductor substrate (200a; Fig. 1; [0015, 0025-0028]); and an additional thermally conductive pillar ({230a, 220a}; Fig. 1; [0027-0028, 0043]) penetrating through the second semiconductor substrate (200a; Fig. 1; [0015, 0025-0028]), wherein the additional thermally conductive pillar ({230a, 220a}; Fig. 1; [0027-0028, 0043]) is electrically and thermally coupled to the thermally conductive pillar ({230b, 210b}; Fig. 1; [0027-0028, 0043]).
3. Claims 1 and 4-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noguchi (US 20060197181 A1; hereinafter Noguchi).
Regarding claim 1, Noguchi teaches a method (see the entire document, specifically Fig. 1+; [0002+], and as cited below), comprising (see alternative rejection for claim 1 above):
forming a first device die (see Fig. 20; [0045+]) comprising:
forming integrated circuits on a first semiconductor substrate (10-4; Fig. 20; see [0045, 0047, 0054]); and
forming a thermally conductive pillar (20; Fig. 20; [0049-0059]) extending into the first semiconductor substrate (10-4); and
attaching a cooling medium (24; Fig. 20; [0055]; thermal conduction layer 24 may be made of any thermally conductive material; see also [0043] of the instant invention where the cooling medium may comprise of thermally conductive material; therefore, it is construed that layer 24 of Noguchi is a cooling medium) over and contacting the first semiconductor substrate (10-4) to form a package, wherein the cooling medium (24; Fig. 20; [0055]; thermal conduction layer 24 may be made of any thermally conductive material) is thermally coupled to the thermally conductive pillar (20; Fig. 20; [0049-0059]).
Regarding claim 4, Noguchi teaches all of the features of claim 1.
Noguchi further teaches wherein the thermally conductive pillar (20; Fig. 20; [0049-0059]) penetrates through the first semiconductor substrate (10-4; Fig. 20; see [0045, 0047, 0054]), and the thermally conductive pillar (20; Fig. 20; [0049-0059]) is in physical contact with the cooling medium (24; Fig. 20; [0055]; thermal conduction layer 24 may be made of any thermally conductive material).
Regarding claim 5, Noguchi teaches all of the features of claim 4.
Noguchi further comprising polishing the first semiconductor substrate (10-4; Fig. 20 in view of Fig. 8-10; see [0070]) to expose a surface of the thermally conductive pillar (20; Fig. 20 in view of Fig. 8-10; see [0070]), wherein a first top surface of the thermally conductive pillar (20; Fig. 20 in view of Fig. 8-10; see [0070]) and a second top surface of the first semiconductor substrate (10-4; Fig. 20 in view of Fig. 8-10; see [0070]) are coplanar.
Regarding claim 6, Noguchi teaches all of the features of claim 4.
Noguchi further comprising, after the polishing, recessing the first semiconductor substrate (10-4; Fig. 20 in view of Fig. 8-10; see [0070-0071]) so that a protruding portion of the thermally conductive pillar (20; Fig. 20 in view of Fig. 8-10; see [0070]) protrudes out of the first semiconductor substrate (10-4; Fig. 20 in view of Fig. 8-10; see [0070-0071]) to extend into the cooling medium (24; Fig. 20 in view of Fig. 8-10; see; [0055, 0070-0071]; thermal conduction layer 24 may be made of any thermally conductive material).
Regarding claim 7, Noguchi teaches all of the features of claim 1.
Noguchi further teaches wherein the thermally conductive pillar (20; Fig. 20 in view of Fig. 8-10; see [0070]) is electrically floating.
Regarding claim 8, Noguchi teaches all of the features of claim 1.
Noguchi further comprising bonding a second device die (10-3; Fig. 20; see [0045, 0047, 0054]) to the first device die (10-4; Fig. 20; see [0045, 0047, 0054]), with the second device (10-3; Fig. 20; see [0045, 0047, 0054]) die being an additional part of the package, wherein the second device die (10-3; Fig. 20; see [0045, 0047, 0054]) comprises: a second semiconductor substrate (10-3; Fig. 20; see [0045, 0047, 0054]); and an additional thermally conductive pillar (20 of 10-3; Fig. 20 in view of Fig. 8-10; see [0070]) penetrating through the second semiconductor substrate (10-3; Fig. 20; see [0045, 0047, 0054]), wherein the additional thermally conductive pillar (20 of 10-3; Fig. 20 in view of Fig. 8-10; see [0070]) is electrically and thermally coupled to the thermally conductive pillar (20; Fig. 20 in view of Fig. 8-10; see [0070]).
Regarding claim 9, Noguchi teaches all of the features of claim 1.
Noguchi further teaches wherein the forming the thermally conductive pillar (20; Fig. 20 in view of Fig. 11-18; see [0074-0081]) comprises: etching the first semiconductor substrate (10-4; Fig. 20 in view of Fig. 11-18; see [0074-0081]) to form an opening; depositing a dielectric liner (2a; Fig. 20 in view of Fig. 11-18; see [0074-0081]) into the opening; and depositing a metallic material (20; Fig. 20 in view of Fig. 11-18; see [0074-0081]) into the opening and on the dielectric liner (2a; Fig. 20 in view of Fig. 11-18; see [0074-0081]).
Regarding claim 10, Noguchi teaches all of the features of claim 9.
Noguchi further comprising, after the depositing the dielectric liner (2a; Fig. 20 in view of Fig. 11-18; see [0074-0081]) and before depositing the metallic material (20; Fig. 20 in view of Fig. 11-18; see [0074-0081]), performing an anisotropic etching process on the dielectric liner (2a; Fig. 20 in view of Fig. 11-18; see [0074-0081]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
4. Claims 2-3 are rejected under 35 U.S.C.103 as being unpatentable over Choi et al. (US 20210005527 A1; hereinafter Choi), in view of Ho et al. (US 20150179607 A1; hereinafter Ho).
Regarding claim 2, Choi teaches all of the features of claim 1.
Choi further teaches wherein the attaching the cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]) comprises: (see below for “dispensing”) the cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]) (see below for “in a flowable form; and curing to solidify”) the cooling medium (160; Fig. 1; [0029-0030, 0039, 0043]).
As noted above, Choi does not expressly disclose “wherein the attaching the cooling medium comprises: dispensing the cooling medium in a flowable form; and curing to solidify the cooling medium”.
However, in the analogous art, Ho teaches a system and method for packaging semiconductor devices ([Abstract]), wherein (Fig. 1+; [0006+]) a first thermal interface material (111; Fig. 2A; [0035]) is in a liquid or semi-solid form. Then a heat treatment is utilized to cure the first thermal interface material such that the first thermal interface material becomes solid ([0035])
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ho’s first thermal interface material in a liquid or semi-solid form and the curing of the first thermal interface material into Choi’s method, and thereby, modified Choi’s (by Ho) method will have wherein the attaching the cooling medium (Choi 160; Fig. 1; [0029-0030, 0039, 0043] in view of Ho 111; Fig. 2A; [0035]) comprises: dispensing the cooling medium (Choi 160; Fig. 1; [0029-0030, 0039, 0043] in view of Ho 111; Fig. 2A; [0035])) in a flowable form; and curing to solidify the cooling medium (Choi 160; Fig. 1; [0029-0030, 0039, 0043] in view of Ho 111; Fig. 2A; [0035])).
The ordinary artisan would have been motivated to modify Choi in the manner set forth above, at least, because this inclusion provides a first thermal interface material in a liquid or semi-solid form that is heat treated in order to cure the first thermal interface material such that the first thermal interface material becomes solid (Ho [0035]), where a solid thermal interface material will not undesirably spill onto other device parts and cause damage such as shorts.
Regarding claim 3, modified Choi (by Ho) teaches all of the features of claim 2.
Modified Choi (by Ho) further comprising attaching a heat sink (Choi 170; Fig. 1; [0020-0021, 0029-0032, 0039-0040]) to the cooling medium (Choi 160; Fig. 1; [0029-0030, 0039, 0043]), wherein the thermally conductive pillar (Choi {230b, 210b}; Fig. 1; [0027-0028, 0043]) penetrates through the cooling medium (Choi 160; Fig. 1; [0029-0030, 0039, 0043]) to contact the heat sink (Choi 170; Fig. 1; [0020-0021, 0029-0032, 0039-0040]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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