Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of Group I, claims 1-13, 21-27 in the reply filed on 6/5/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statements filed 9/30/24; 10/26/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 11/22/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-10, 12-13, 21-27 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chen et al. (US Patent Publication No. 2022/0223553).
Referring to figures 1-41, Chen et al. teaches an integrated circuit package, comprising:
a first die (100);
a first gap-fill layer (E1) along sidewalls of the first die;
a first bonding layer (BF1) on the first die and the first gap-fill layer; and
a first die connector (BP/BV) in the first bonding layer, wherein the first die connector is directly over an interface between the first die and the first gap-fill layer (see figure 5).
Regarding to claim 2, the first die (100) comprises a first semiconductor substrate, wherein the first die connector is in contact with the first semiconductor substrate and the first gap-fill layer (see figure 5).
Regarding to claim 3, the first die connector (BP/BV) is electrically isolated from circuitry of the first die (100, see figures 34-39).
Regarding to claim 4, a second die connector (BP11-12) and a third die connector (BP15-16) in the first bonding layer (BF1), wherein the first die connector (BP13-14) is between the second die connector and the third die connector, wherein the second die connector and the third die connector are the closest die connectors to the first die connector along a first direction, wherein the second die connector is electrically coupled to circuitry of the first die, and wherein the third die connector is over the first gap fill layer, the third die connector being electrically isolated from the circuitry of the first die (see figures 34-39).
Regarding to claim 6, the second die connector (BP11-12) is spaced apart from the first die connector (BP13-14) by a first distance and the third die connector (BP15-16) is spaced apart from the first die connector by a second distance, and wherein the first distance is equal to the second distance (see figures 34-39).
Regarding to claim 7, a second die (200) bonded to the first bonding layer (BF1), and a second gap-fill layer (E2) on the first bonding layer (BF1), the second gap fill layer (E2) extending along sidewalls of the second die (200, see figure 34).
Regarding to claim 8, an integrated circuit package, comprising:
a first die (100), wherein the first die further comprises a first semiconductor substrate (102);
a first gap-fill layer (E1) on sidewalls of the first die;
a first bonding layer (BF1) on the first gap-fill layer and the first semiconductor substrate;
a first die connector (BP/BV) in the first bonding layer, wherein the first die connector is in contact with an interface between the first die and the first gap-fill layer; and
a second die (200) comprising a second bonding layer (BF2) and a second die connector (BP21-22) in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer and the second die connector is bonded to the first die connector (see figures 34-39).
Regarding to claim 9, a coefficient of thermal expansion of the first gap-fill layer is different from a coefficient of thermal expansion of the first semiconductor substrate (see paragraphs# 19, 28).
Regarding to claim 10, the interface between the first die (100) and the first gap-fill layer (E1) divides the first die connector into two portions of a same size in a top-down view (see figures 20-21).
Regarding to claim 12, the first die connector is a dummy die connector (BP/BV, see figure 20).
Regarding to claim 13, a second gap-fill layer (E2) on sidewalls of the second die (200), wherein the second gap-fill layer extends over a third die connector (BP13/14) in the first bonding layer (BF1), wherein the third die connector is in contact with an interface between the second die (200) and the second gap-fill layer (E2, see figures 20-39).
Regarding to claim 21, an integrated circuit package, comprising:
a first die (100), wherein the first die comprises a first semiconductor substrate (102);
a first gap-fill layer (E1) on sidewalls of the first die, wherein the first gap-fill layer comprises a dielectric material (see paragraph# 28);
a first bonding layer (BF1) on the first gap-fill layer and the first semiconductor substrate;
a first die connector (BP/BV) in the first bonding layer, wherein the first die overlaps an interface between the first semiconductor substrate and the first gap-fill layer in a top- down view (see figures 9, 34); and
a second die, wherein the second die (200) comprises a second semiconductor substrate (202), a second bonding layer (BF2), and a second die connector (BP22-21) in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer by dielectric-to-dielectric bonding (BF1-BF2) and the second die connector is bonded to the first die connector by metal-to-metal bonding(BV1-BV2, see figure 8).
Regarding to claim 22, the first die connector contacts (BV1) the first semiconductor substrate (102) and the first gap-fill layer (E1, see figures 9).
Regarding to claim 23, a third die (100 on the right side) beside the first die, wherein the third die comprises a third semiconductor substrate (102), wherein a first portion of the first gap-fill layer (E1) is between the first die and the third die (100), and wherein the first bonding layer (BF1) is on the third semiconductor substrate (102); and a third die connector (BF/BV) in the first bonding layer (BF1), wherein the third die connector overlaps an interface between the third semiconductor substrate and the first gap-fill layer in the top-down view (see figure 9).
Regarding to claim 24, the third die connector (BF/BV) contacts the third semiconductor substrate and the first gap-fill layer (see figures 34-39).
Regarding to claim 25, a fourth die connector (BF/BV) in the first bonding layer, wherein the fourth die connector is laterally between the first die and the third die (see figure 35).
Regarding to claim 26, the first die connector (BF/BV), the second die connector, and the third die connector are isolated from circuitry of the first die, circuitry of the second die, and circuitry of the third die (see figures 34-39).
Regarding to claim 27, a third die connector (BF/BV) in the first bonding layer (BF1), wherein a first conductive via (103) of the first die extends through the first semiconductor substrate and contacts the third die connector (see figures 34-39).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Patent Publication No. 2022/0223553) as applied to claims 1-4, 6-10, 12-13, 21-27 above.
Referring to figures 1-41, Chen et al. teaches an integrated circuit package, comprising:
a first die (100);
a first gap-fill layer (E1) along sidewalls of the first die;
a first bonding layer (BF1) on the first die and the first gap-fill layer; and
a first die connector (BP/BV) in the first bonding layer, wherein the first die connector is directly over an interface between the first die and the first gap-fill layer (see figure 5).
However, the reference does not clearly teach the specific distance between the die connectors (in claim 5) and the interface between the first die and the first gap-fill layer divides the first die connector into two portions of different sizes in a top-down view (in claim 11).
In particular, Chen et al. suggest that the second die connector (BP11-12) is spaced apart from the first die connector (BP13-14) by a first distance and the third die connector (BP15-16) is spaced apart from the first die connector by a second distance (see figures 34-39). Th interface between the first die (100) and the first gap-fill layer (E1) divides the first die connector into two portions in a top-down view (see figures 20-21).
It would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made to optimize the specific distance between the die connectors (in claim 5) and the interface between the first die and the first gap-fill layer divides the first die connector into two portions of different sizes in a top-down view, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the specific distance between the die connectors (in claim 5) and the interface between the first die and the first gap-fill layer divides the first die connector into two portions of different sizes in a top-down view) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Therefore, it is obvious to a person of ordinary skill in the requisite art at the time of the invention was filed to form the specific distance between the die connectors and the interface between the first die and the first gap-fill layer divides the first die connector into two portions of different sizes in a top-down view in Chen et al. because choosing an optimum distance and the size of the die connector is known in the art to form an optimum semiconductor device.
The additional references cited in form PTO-892 show further analogous device. Specifically references (Yu et al., 2024/0413136; Hsu et al, 2024/0079391; Yang et al. 2023/0290694; Chen et al. 2023/0095134; Chen et al. 2022/0271012) are particularly relevant to claimed device and manufacture which recited in claims 1-13, 21-27. Yu et al., Hsu et al., Yang et al. and Chen et al. teach a semiconductor device having a first die, a first gap-fill layer along sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer and a first die connector. These references are deemed relevant and should be carefully reviewed before any amendment is filed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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