Prosecution Insights
Last updated: April 19, 2026
Application No. 18/482,717

DISPLAY DEVICE

Non-Final OA §102
Filed
Oct 06, 2023
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
85%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
648 granted / 845 resolved
+8.7% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI et al. (US PG Pub 2018/0102400, hereinafter Choi). Regarding claim 1, figures 4 and 7 of Choi disclose a display device comprising: a substrate (110); a first voltage line (172) in a first metal layer on the substrate and extending in a first direction; a horizontal gate line (152) in a second metal layer on the first metal layer and extending in a second direction crossing the first direction; a pixel circuit of a first pixel (shown in figure 4) and a pixel circuit of a second pixel (pixel adjacent to that in figure 4 in the Y-direction) in the first metal layer, the second metal layer, and an active layer (131) between the first and second metal layers; and a shielding line (158) connected to the first voltage line and extending in the second direction, the shielding line being located between the pixel circuit of the first pixel and the pixel circuit of the second pixel (irrespective of which parts of the adjacent pixel circuits are taken, some parts of the adjacent pixels will always be on opposites sides of the shielding electrode, e.g. T5 of adjacent pixels). Allowable Subject Matter Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 10-20 are allowed. Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a first shielding line in the first metal layer and integrally formed with the first voltage line; and a second shielding line in the second metal layer and overlapping the first shielding line”. Regarding claim 15, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the shielding line being integrally formed with the first voltage line, and located between the pixel circuit of the first pixel and the pixel circuit of the second pixel”. Regarding claim 18, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a first shielding line in the first metal layer and integrally formed with the first voltage line; and a second shielding line in the second metal layer and overlapping the first shielding line”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Oct 06, 2023
Application Filed
Jan 12, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604693
METHOD OF MANUFACTURING CHIPS
2y 5m to grant Granted Apr 14, 2026
Patent 12598821
CHIP PACKAGE STRUCTURE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593717
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12581982
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 17, 2026
Patent 12582016
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
85%
With Interview (+8.4%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allow rate.

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