Prosecution Insights
Last updated: May 29, 2026
Application No. 18/482,849

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Non-Final OA §103
Filed
Oct 07, 2023
Priority
Oct 08, 2022 — CN 202211222809.X
Examiner
NGUYEN, KHIEM D
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1896 granted / 2213 resolved
+17.7% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
40 currently pending
Career history
2267
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.8%
+29.8% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2213 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The IDS filed on December 25th, 2024 has been considered. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor device comprising a shielding layer on an encapsulant and method for making the same. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 6, and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (U.S. Pub. 2011/0006408). In re claim 1, Liao discloses a method for making a semiconductor device, comprising: providing a package comprising: a substrate 100 comprising a top substrate surface and a bottom substrate surface (see paragraph [0023] and fig. 1A); an electronic component 120 mounted on the top substrate surface (see paragraph [0024] and fig. 1B); and a first encapsulant 130 disposed on the top substrate surface and encapsulating the electronic component 120 (see paragraph [0025] and fig. 1C); forming a fiducial mark 135 in the first encapsulant 130 (see paragraph [0026] and figs. 1D and 1D’); and forming a first shielding layer 140 on the first encapsulant 130, wherein the first shielding layer 140 is above the electronic component 120 (see paragraph [0029] and fig. 1F). PNG media_image1.png 490 756 media_image1.png Greyscale PNG media_image2.png 262 754 media_image2.png Greyscale Liao is silent to wherein the first shielding layer is at a predetermined distance from the fiducial mark. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to modify the semiconductor device of Liao to selectively deposit the first shielding layer so that the first shielding layer is at a predetermined distance from the fiducial mark since when the first shielding layer is selectively deposited and being spaced apart from the fiducial mark, less material is required for forming the first shielding layer and further simplifying the singulation process for separating the semiconductor device from the package since the singulation process does not required to saw or cut through the first shielding layer which in turn can effectively simplify the manufacturing process and save manufacturing time and material costs, thereby significantly reducing the manufacturing cost. In re claim 2, as applied to claim 1 above, Liao discloses wherein forming the fiducial mark 135 in the first encapsulant 130 comprises: forming a groove 135 in the first encapsulant 130 at a singulation channel 137 of the package (see paragraphs [0026], [0028] and figs. 1D and 1E). In re claim 3, as applied to claim 2 above, Liao discloses wherein forming the groove 135 in the first encapsulant 130 comprising: forming the groove in the first encapsulant 130 using a saw blade or a laser cutting tool (see paragraph [0026] and figs. 1E and 1F, note that Liao discloses that the groove is formed via a saw blade). In re claim 6, as applied to claim 1 above, Liao discloses wherein a projection of the first shielding layer 140 onto the top substrate surface covers the electronic component 120 (see paragraphs [0024], [0029] and fig. 1F). In re claim 10, Liao discloses a semiconductor device, comprising: a substrate 100 comprising a top substrate surface and a bottom substrate surface (see paragraph [0023] and fig. 1A); an electronic component 120 mounted on the top substrate surface (see paragraph [0024] and fig. 1B); a first encapsulant 130 disposed on the top substrate surface and encapsulating the electronic component 120 (see paragraph [0025] and fig. 1C); a fiducial mark 135 formed in the first encapsulant 130 (see paragraph [0026] and figs. 1D and 1D’); and a first shielding layer 140 formed on the first encapsulant 130, wherein the first shielding layer 140 is above the electronic component 120 (see paragraph [0029] and fig. 1F). Liao is silent to wherein the first shielding layer is at a predetermined distance from the fiducial mark. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to modify the semiconductor device of Liao to selectively deposit the first shielding layer so that the first shielding layer is at a predetermined distance from the fiducial mark since when the first shielding layer is selectively deposited and being spaced apart from the fiducial mark, less material is required for forming the first shielding layer and further simplifying the singulation process for separating the semiconductor device from the package since the singulation process does not required to saw or cut through the first shielding layer which in turn can effectively simplify the manufacturing process and save manufacturing time and material costs, thereby significantly reducing the manufacturing cost. In re claim 11, as applied to claim 10 above, Liao discloses wherein the fiducial mark 135 comprises a groove formed in the first encapsulant 130 at a singulation channel 137 of the substrate 100 (see paragraphs [0026], [0028] and figs. 1D and 1E). In re claim 12, as applied to claim 10 above, Liao discloses wherein a projection of the first shielding layer 140 onto the top substrate surface covers the electronic component 120 (see paragraphs [0024], [0029] and fig. 1F). Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (U.S. Pub. 2011/0006408), as applied to claim 1 above, and further in view of Hoang et al. (U.S. Pub. 2016/0286647). In re claim 4, as applied to claim 1 above, Liao discloses wherein forming the first shielding layer on the first encapsulant comprising forming the first shielding layer on the first encapsulant using a spray coating method, a plating method, or a sputtering method (see paragraph [0029] and fig. 1F). However, Liao is silent to wherein forming the first shielding layer on the first encapsulant comprising: forming the first shielding layer on the first encapsulant using an aerosol jetting apparatus. However, Hoang discloses in a same field of endeavor, a method for making a semiconductor device, including, inter-alia, providing a package comprising a substrate 3220 comprising a top substrate surface and a bottom substrate surface, an electronic component 3210 mounted on the top substrate surface; a first encapsulant 3240 disposed on the top substrate surface, and forming a first shielding layer 3250 on the first encapsulant 3240, wherein forming the first shielding layer 3250 on the first encapsulant 3240 comprising: forming the first shielding layer 3250 on the first encapsulant 3240 using plating, sputtering, 3-D, aerosol jetting apparatus, or other type of printing, vapor deposition, or other technique (see paragraph [0091] and fig. 32). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hoang into the method for making the semiconductor device of Liao in order to enable the step of forming the first shielding layer on the first encapsulant comprising: forming the first shielding layer on the first encapsulant using an aerosol jetting apparatus in Liao to be performed because Hoang suggested it is well-known in the art to form the first shielding layer using an aerosol jetting apparatus and techniques such as plating, sputtering, and aerosol jetting can be interchangeable for forming the first shielding layer. In re claim 5, as applied to claim 4 above, Liao and Hoang are silent to wherein forming the first shielding layer on the first encapsulant using the aerosol jetting apparatus comprising: inspecting the package to determine a location of the fiducial mark and a distance between the fiducial mark and the electronic component; and controlling the aerosol jetting apparatus to form the first shielding layer based on the location of the fiducial mark and the distance between the fiducial mark and the electronic component. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to inspect the package to determine a location of the fiducial mark and a distance between the fiducial mark and the electronic component so as to control the aerosol jetting apparatus to form the first shield layer based on the location of the fiducial mark and the distance between the fiducial mark and the electronic component in order to form the first shielding layer with sufficient thickness so as to effectively protecting the electronic component from electromagnetic interference. Claim(s) 7-9, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (U.S. Pub. 2011/0006408), as applied to claims 1 and 10 above, respectively, and further in view of Yen et al. (U.S. Pub. 2014/0252595). In re claim 7, as applied to claim 1 above, Liao discloses wherein the method further comprising singulating the semiconductor device from the package along a singulation channel 137 of the package (see paragraphs [0028], [0031] and figs. 1F and 1G) but is silent to wherein the method further comprising forming a second encapsulant on the first encapsulant to cover the fiducial mark and the first shielding layer; and forming a second shielding layer to cover the semiconductor device. However, Yen discloses in a same field of endeavor, a method for making a semiconductor device, comprising: providing a package comprising: a substrate 110 comprising a top substrate surface and a bottom substrate surface (see paragraph [0027] and fig. 1A); an electronic component 120 mounted on the top substrate surface (see paragraph [0026] and fig. 1A); and a first encapsulant 131 disposed on the top substrate surface and encapsulating the electronic component 120 (see paragraph [0029] and fig. 1A); forming a first shielding layer 140 on the first encapsulant 131 (see paragraph [0026] and fig. 1A), wherein the method further comprising forming a second encapsulant 132 on the first encapsulant 131 to cover the first shielding layer 140 (see paragraph [0029] and fig. 1A); and forming a second shielding layer 173 to cover the semiconductor device (see paragraph [0036] and fig. 1A). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yen into the method for making the semiconductor device of Liao in order to enable the step of forming a second encapsulant on the first encapsulant to cover the fiducial mark and the first shielding layer; and forming a second shielding layer to cover the semiconductor device in Liao to be performed in order to reduce package size and shorter RF signal transmission paths (see paragraph [0025] of Yen, note that, when the second encapsulation of Yen is applied to the semiconductor device of Liao, the second encapsulant would be covering the fiducial mark and the first shielding layer). In re claim 8, as applied to claim 7 above, Liao in combination with Yen discloses wherein the second shielding layer 173 conforms to a shape of the semiconductor device (see paragraph [0036] and fig. 1A of Yen). In re claim 9, as applied to claim 7 above, Liao in combination with Yen discloses wherein the second encapsulant 132 comprises an epoxy molding compound filled with one or more high-k dielectric materials (see paragraph [0029] of Yen). Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 13, as applied to claim 10 above, Liao is silent to wherein the semiconductor device further comprising a second encapsulant formed on the first encapsulant and covering the fiducial mark and the first shielding layer. However, Yen discloses in a same field of endeavor, a semiconductor device, comprising a package comprising: a substrate 110 comprising a top substrate surface and a bottom substrate surface (see paragraph [0026] and fig. 1A); an electronic component 120 mounted on the top substrate surface (see paragraph [0026] and fig. 1A); and a first encapsulant 131 disposed on the top substrate surface and encapsulating the electronic component 120 (see paragraph [0029] and fig. 1A); a first shielding layer 140 on the first encapsulant 131 (see paragraph [0034] and fig. 1), and a second encapsulant 132 on the first encapsulant 131 to cover the first shielding layer 140; and a second shielding layer 173 covering the semiconductor device (see paragraphs [0029], [0036] and fig. 1A). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yen into the semiconductor device of Liao in order to enable a second encapsulant formed on the first encapsulant and covering the fiducial mark and the first shielding layer in Liao to be formed in order to reduce package size and shorter RF signal transmission paths (see paragraph [0025] of Yen, note that, when the second encapsulation of Yen is applied to the semiconductor device of Liao, the second encapsulant would be covering the fiducial mark and the first shielding layer). In re claim 14, as applied to claim 13 above, Liao in combination with Yen discloses wherein the second encapsulant 132 comprises an epoxy molding compound filled with one or more high-k dielectric materials (see paragraph [0029] of Yen). Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jung et al. U.S. Patent 10,629,565 April 21st, 2020. Yamamoto et al. U.S. Pub. 2018/0108618 April 19, 2018. Lin et al. U.S. Pub. 2015/0155248 June 4, 2015. An et al. U.S. Patent 8,410,584 April 2, 2013. Arnold U.S. Pub. 2006/0272857 December 7, 2006. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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Prosecution Timeline

Oct 07, 2023
Application Filed
Dec 10, 2025
Non-Final Rejection (signed) — §103
Jan 26, 2026
Non-Final Rejection mailed — §103
Apr 23, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2213 resolved cases by this examiner. Grant probability derived from career allowance rate.

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