Prosecution Insights
Last updated: April 19, 2026
Application No. 18/482,954

INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME

Non-Final OA §102
Filed
Oct 09, 2023
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
85%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
648 granted / 845 resolved
+8.7% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species I in the reply filed on 2/4/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 3, 8, 11, 13, and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/4/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 4-7, 9, 10, 12, 14-15, 17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipate by KWON et al. (US PG Pub 2023/0144388, hereinafter Kwon). Regarding claim 1, figures 3A, 6, and 8 of Kwon disclose a semiconductor package comprising: a substrate (110); an integrated circuit package component (133) bonded to the substrate, wherein the integrated circuit package component comprises a semiconductor die (¶ 37); and a ring structure (155/157/1515/1535) on the substrate, wherein the ring structure encircles the integrated circuit package component in a top-down view, and wherein the ring structure comprises: a first attached segment (1515) attached to the substrate by an adhesive (181, see figure 3A), wherein the first attached segment is spaced apart from the package component (133) by a first distance; a second attached segment (1535) attached to the substrate by the adhesive (181, see figure 3A), wherein the second attached segment is spaced apart from the package component (133) by a second distance; and a first suspended segment (155) between the first attached segment and the second attached segment, wherein the first suspended segment is suspended over the substrate (figure 8, ¶ 69), wherein the first suspended segment is spaced apart from the package component by a third distance, and wherein the third distance is different from the first distance and the second distance (see figure 6). Regarding claim 2, figure 6 of Kwon discloses the third distance is smaller than the first distance and the second distance. Regarding claim 4, figures 3A, 6, and 8 of Kwon disclose a width of the first suspended segment (155, measured vertically in figure 6) is smaller than a width of the first attached segment (1515) and a width of the second attached segment (1535, measured horizontally in figure 6). Regarding claim 5, figures 3A, 6, and 8 of Kwon disclose a height of the first suspended segment (155) is smaller than a height of the first attached segment (1515) and a height of the second attached segment (1525). Note: The device can be tilted in such a way as to achieve the claimed height relation between the first suspended segment and the first/second attached segments. Regarding claim 6, figures 3A, 6, and 8 of Kwon disclose the first attached segment (1515), the second attached segment (1525), and the first attached segment (1515) are a same piece of continuous material. Regarding claim 7, Kwon discloses the first attached segment (1515), the second attached segment (1535), and the first suspended segment (155) comprise copper (¶ 38). Regarding claim 9, figures 3A, 6, and 8 of Kwon disclose: a substrate (110) comprising a first edge and a second edge, wherein the first edge intersects with the second edge; an integrated circuit package component (133) bonded to the substrate, wherein the package component comprises a semiconductor die (¶ 37); an underfill (175) between the integrated circuit package component and the substrate; and a stiffener ring (155/157/1515/1535) on the substrate, wherein the stiffener ring encircles the integrated circuit package component in a top-down view, and wherein a first portion of the stiffener ring extends along the first edge of the substrate, the first portion comprising: a first attached segment (1515) with a first width (measured horizontally in figure 6), wherein a bottom surface of the first attached segment is covered by an adhesive (181); a second attached segment (1535) with a second width (measured horizontally in figure 6), wherein a bottom surface of the second attached segment is covered by the adhesive (181); and a first suspended segment (155) extending from the first attached segment to the second attached segment, the first suspended segment having a third width (measured vertically in figure 6), wherein the third width is smaller than the first width and the second width, wherein a bottom surface of the first suspended segment is free of the adhesive (¶ 69). Regarding claim 10, figure 6 of Kwon discloses the first suspended segment (155) protrudes towards the integrated circuit package component (133) from an inner sidewall of the first attached segment (1515) and an inner sidewall of the second attached segment (1535). Note: Being a three-dimensional object, the first suspended segment can be said to “protrude towards” the integrated circuit package at least by a distance of the thickness of the layer (measured horizontally in figure 6). Regarding claim 12, figures 3A, 6, and 8 of Kwon disclose a second portion of the stiffener ring extends along the second edge of the substrate, the second portion comprising: a third attached segment (other end of 1515) with a fourth width (measured horizontally in figure 6), wherein a bottom surface of the third attached segment is covered by the adhesive (181); a fourth attached segment (other end of 1535) with a fifth width (measured horizontally in figure 6), wherein a bottom surface of the fourth attached segment is covered by the adhesive (181); and a second suspended segment (157) extending from the third attached segment to the fourth attached segment, the second suspended segment having with a sixth width (measured vertically in figure 6), wherein the sixth width is smaller than the fourth width and the fifth width, wherein a bottom surface of the second suspended segment is free of the adhesive (¶ 69). Regarding claim 14, figures 3A, 6, and 8 of Kwon disclose a method of manufacturing a semiconductor package, the method comprising: bonding an integrated circuit package component (133) to a substrate (110), wherein the integrated circuit package component comprises a semiconductor die (¶ 37), and wherein the substrate comprises a first edge and a second edge, wherein the first edge intersects with the second edge; placing an underfill (175) between the integrated circuit package component and the substrate; and attaching a ring structure (155/157/1515/1535) to the substrate, wherein the ring structure encircles the integrated circuit package component in a top-down view, and wherein a first portion of the ring structure extends along the first edge of the substrate, the first portion comprising: a first attached segment (1515) connected to the substrate by an adhesive (181), wherein the first attached segment is spaced apart from the integrated circuit package component by a first distance; a second attached segment (1535) connected to the substrate by the adhesive (181), wherein the second attached segment is spaced apart from the integrated circuit package component by a second distance; and a first suspended segment (155) between the first attached segment and the second attached segment, wherein the first suspended segment is in contact with the first attached segment and the second attached segment, wherein the first suspended segment is separated from the substrate by a first cavity (figure 8, ¶ 69), wherein the first suspended segment is spaced apart from the integrated circuit package component by a third distance, and wherein the third distance is different from the first distance and the second distance (see figure 6). Regarding claim 15, figure 6 of Kwon discloses the third distance is smaller than the first distance and the second distance. Regarding claim 17, figures 3A, 6, and 8 of Kwon disclose a height of the first suspended segment (155) is smaller than a height of the first attached segment (1515) and a height of the second attached segment (1525). Note: The device can be tilted in such a way as to achieve the claimed height relation between the first suspended segment and the first/second attached segments. Regarding claim 19, figures 3A, 6, and 8 of Kwon disclose a second portion of the ring structure extends along the second edge of the substrate (110), the second portion comprising: a third attached segment (other end of 1515) connected to the substrate by the adhesive (181); a fourth attached segment (other end of 1535) connected to the substrate by the adhesive; and a second suspended segment (157) between the third attached segment and the fourth attached segment, wherein the second suspended segment is in contact with the third attached segment and the fourth attached segment, and wherein the second suspended segment is separated from the substrate by a second cavity (¶ 69). Allowable Subject Matter Claims 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

Oct 09, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604693
METHOD OF MANUFACTURING CHIPS
2y 5m to grant Granted Apr 14, 2026
Patent 12598821
CHIP PACKAGE STRUCTURE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593717
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12581982
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 17, 2026
Patent 12582016
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
85%
With Interview (+8.4%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allow rate.

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