Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/09/2023 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 7-9 and 14-16 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claims 5 and 14 the feature that a source contact and a ground terminal are separated "by a predetermined distance" is vague and broader than supported by the description. Since no particular separation distance is presently defined, the pending definition merely states that said two items do not touch each other. However, from the disclosure in fig. 5B and par. [0080] it appears that the feature might aim to define a separation of said items substantially by a thickness Dg of the package substrate on which the inductance is formed.
Also, the feature that one or more conductive connection patterns in the package substrate having respective shapes and/or sizes is vague and broader than supported by the description. Since no particular size and shape is presently defined, it appears from Figures 4b and 5C, the shape appears to be only conical or cylindrical.
Claims 7, 8 and 16 are unclear insofar as the features of an input low pass and input high pass may be combined. It is clear that a low pass filter and a high pass filter may generally be connected in series to form a band pass. However, such a series connection requires that respective cut-off frequencies leave a common band. In the present case a respective overlap seems to be excluded by the definitions that the stabilized frequency of the low pass is lower than the first operating frequency and the stabilized frequency of the high pass is higher than the first operating frequency.
The feature of claims 9 and 16 that "a unit gate width (...) is based on the first operating frequency" is entirely unclear. It appears that the intention is to define a consideration of the gate finger resistance in the provision of a stabilization at a desired operating frequency (see pars. [0069]-[0070)). However, it is generally impossible to evaluate such a definition for a given prior art document. If a known circuit with gate fingers is stabilized at an operating frequency (as defined by the independent claims), the gate finger resistance can inherently be seen as being "based on" said frequency.
Claims 5-9, and 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 5 and 14 the optional feature that a source contact and a ground terminal are separated "by a predetermined distance" is vague and broader than supported by the description. Since no particular separation distance is presently defined, the pending definition merely states that said two items do not touch each other. However, from the disclosure in fig. 5B and par. [0080] it appears that the feature might aim to define a separation of said items substantially by a thickness Dg of the package substrate on which the inductance is formed.
Also, the feature that one or more conductive connection patterns in the package substrate having respective shapes and/or sizes is vague and broader than supported by the description. Since no particular size and shape is presently defined, it appears from Figures 4b and 5C, the shape appears to be only conical or cylindrical.
In claims 6 and 15 the feature that the inductance adjustment element is configured to provide the entirety of the predetermined inductance is vague and unclear for the following reasons: Firstly, the amount of "predetermined inductance" is not defined and as such; when evaluating the prior art, the value of a "predetermined inductance" can always be set to the value of a given adjustment element. Secondly it is clear that connecting elements (e.g. bump connectors) will always have a certain contribution to the total inductance such that an "entirety of predetermined inductance" can always only be attained if said connectors are artificially seen as being comprised by the inductance adjustment element.
Claims 7, 8 and 16 are unclear insofar as the features of an input low pass and input high pass may be combined. It is clear that a low pass filter and a high pass filter may generally be connected in series to form a band pass. However, such a series connection requires that respective cut-off frequencies leave a common band. In the present case a respective overlap seems to be excluded by the definitions that the stabilized frequency of the low pass is lower than the first operating frequency and the stabilized frequency of the high pass is higher than the first operating frequency.
The feature of claims 9 and 16 that "a unit gate width (...) is based on the first operating frequency" is entirely unclear. It appears that the intention is to define a consideration of the gate finger resistance in the provision of a stabilization at a desired operating frequency (see pars. [0069]-[0070)). However, it is generally impossible to evaluate such a definition for a given prior art document. If a known circuit with gate fingers is stabilized at an operating frequency (as defined by the independent claims), the gate finger resistance can inherently be seen as being "based on" said frequency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 12- 15, 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lahbib et al, US 20200365619 .
Lahbib teaches, pars. [0061]-[0068] as well as fig. 12. a radio frequency (RF) transistor amplifier package (80), comprising: a transistor die comprising a semiconductor structure ("on silicon" comprising a micro-printed GaN chiplet thereon) including a plurality of transistors (76, 78) and gate, drain, and source contacts electrically coupled thereto; and an inductance adjustment element (Ls) that is electrically coupled between the source contacts and an electrical ground member, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die (see par. [0068]: "unconditionally stable up to 10 GHz").
2. The RF transistor amplifier package of Claim 1, further comprising:
a package substrate comprising input, output, and ground terminals,
wherein the transistor die is on the package substrate and the ground terminal is electrically coupled to the electrical ground member. (see para 66 and Figure 12)
3. The RF transistor amplifier package of Claim 2, wherein the transistor die is mounted on a surface of the package substrate in a flip chip configuration with the source contacts adjacent the surface of the package substrate. (see para 66 and Figure 12)
Lahbib further teaches:
12. The RF transistor amplifier package of Claim 1, wherein the semiconductor structure comprises gallium nitride and/or silicon carbide. (para 45)
13. A method of fabricating a radio frequency (RF) transistor amplifier package, the method comprising:
providing a transistor die comprising a semiconductor structure including a plurality of transistors and gate, drain, and source contacts electrically coupled thereto; and
providing an inductance adjustment element that is electrically coupled between the source contacts and an electrical ground member, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die. (see Figure 12 and para 66 along with above explanation of claim 1)
14. The method of Claim 13, further comprising:
providing the transistor die on a package substrate comprising input, output, and ground terminals, wherein the ground terminal is electrically coupled to the electrical ground member. (see para 66 and Figure 12)
15. The method of Claim 14, further comprising:
mounting the transistor die on a surface of the package substrate in a flip chip configuration with the source contacts adjacent the surface of the package substrate. (see para 66 and Figure 12)
24. The method of Claim 13, wherein the semiconductor structure comprises gallium nitride and/or silicon carbide. (para 45)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) s 4, 6 and 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lahbib as applied to claim 1 above, and further in view of Narathong et al, US 2010/0033253.
Lahbib fails to teach:
4. The RF transistor amplifier package of Claim 2, wherein the inductance adjustment element is configured to provide a predetermined inductance and is external to the transistor die.
6. The RF transistor amplifier package of Claim 4, wherein the predetermined inductance is free of inductance contributions from conductive vias that extend in the semiconductor structure of the transistor die.
16. The method of Claim 14, wherein the inductance adjustment element is configured to provide a predetermined inductance and is external to the transistor die.
18. The method of Claim 16, wherein the predetermined inductance is free of inductance contributions from conductive vias that extend in the semiconductor structure of the transistor die.
Narathong pars. [0027]-[0040] as well as fig. 4, discloses in fig. 4 a radio frequency (RF) transistor amplifier package, comprising: a transistor die ("chip") comprising a semiconductor structure including a plurality of transistors (MNE, MN1, ...) and gate, drain, and source contacts electrically coupled thereto; and an inductance adjustment element (Ls, Lp,) that is electrically coupled between the source contacts and an electrical ground member, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because [the] parasitic series resistance associated with the peaking inductor 300 is designed to be as small as possible. This is to minimize the gain loss associated with source degeneration of the amplifier 200, as well as to minimize DC current dissipation by the peaking inductor 300. (para 37, Narathong)
Claim(s) 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lahbib as applied to claim 1 above, and further in view of Leong et al, US 20150364418 A1.
Lahbib fails to teach:
5. The RF transistor amplifier package of Claim 4, wherein the inductance adjustment element comprises at least one of:
a plurality of conductive bumps or pillars;
a dimension that is configured to separate the source contacts and the ground terminal by a predetermined distance;
one or more conductive connection patterns in the package substrate having respective shapes and/or sizes; or
a patterning of the electrical ground member.
17. The method of Claim 16, wherein providing the inductance adjustment element comprises at least one of:
providing a plurality of conductive bumps or pillars;
providing a dimension that is configured to separate the source contacts and the ground terminal by a predetermined distance;
providing one or more conductive connection patterns in the package substrate having respective shapes and/or sizes; or
providing a patterning of the electrical ground member.
Leong discloses in fig. 4 a flip-chip package (250) with a transistor die (252+270) and an off-chip inductor (254), wherein said inductor comprises bumps/pillars, a separation between die terminals and package ground terminals (defined by the thickness of layer 254) as well as a conductive connection pattern which defines said inductor and respective external connections.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the above references because, [t]he second substrate 262 may have any number of metallization layers and/or insulation layers disposed (i) on the second substrate 262, and/or (ii) under the second substrate 262 between the second substrate and the intermediate layer 256. The metallization layers may include passive devices (e.g., the passive devices shown in FIGS. 1-2) and/or interconnect devices (e.g., couplers, jumpers, traces, etc.) Leong para (109)
Claim(s) 8-10 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lahbib as applied to claim 1 above, and further in view of KR 20180059721.
Lahbib fails to teach:
8. The RF transistor amplifier package of Claim 7, wherein the inductance adjustment element is configured to provide an entirety of the predetermined inductance.
9. The RF transistor amplifier package of Claim 4, further comprising:
a high pass impedance matching circuit that is electrically coupled between the input terminal and the gate contact, and is configured to provide the stability factor K of greater than or equal to 1 for a second operating frequency range that is higher than the first operating frequency range.
10. The RF transistor amplifier package of Claim 4, further comprising:
a low pass impedance matching circuit that is electrically coupled between the input terminal and the gate contact, and is configured to provide the stability factor K of greater than or equal to 1 for a third operating frequency range that is lower than the first operating frequency range.
20. The method of Claim 16, wherein the inductance adjustment element is configured to provide an entirety of the predetermined inductance.
21. The method of Claim 16, further comprising:
providing a high pass impedance matching circuit that is electrically coupled between the input terminal and the gate contact, and is configured to provide the stability factor K of greater than or equal to 1 for a second operating frequency range that is higher than the first operating frequency range.
22. The method of Claim 16, further comprising:
providing a low pass impedance matching circuit that is electrically coupled between the input terminal and the gate contact, and is configured to provide the stability factor K of greater than or equal to 1 for a third operating frequency range that is lower than the first operating frequency range.
‘721 teaches in fig. 1 an RF amplifier circuit (100) comprising an amplifying unit (130) as well as an input circuit (110+120) comprising impedance matching, filtering (here: high pass filtering 120) as well as stabilization (see par. [0022]). Attention is in particular drawn to fig. 10, which explicitly discloses unconditional stabilization (K >= 1) over the entire relevant frequency range, provided by the disclosed input filter and stabilization circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because a stabilization device includes an RC parallel connection part and an inductive element. The RC parallel connection part includes a resistive element connected between a first node and a second node, and a capacitive element connected in parallel to the resistive element and outputs a signal through a second node based on a signal received through the first node. The inductive element is connected between the first node and a third node. Accordingly, the present invention can improve the stability of an amplifier. (abstract ‘271)
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lahbib as applied to claim 1 above, and further in view Compoche et al, US 20210313293 A1.
Lahbib fails to teach:
7. The RF transistor amplifier package of Claim 4, wherein the transistor die comprises a plurality of source fingers on the semiconductor structure, and is free of conductive vias that are electrically coupled to the source fingers.
19. The method of Claim 16, wherein the transistor die comprises a plurality of source fingers on the semiconductor structure, and is free of conductive vias that are electrically coupled to the source fingers.
Compoche teaches:
As shown in FIG. 1C, the RF transistor amplifier die 110 comprises a Group III nitride-based HEMT RF transistor amplifier that has a plurality of unit cell transistors 116 that each include a gate finger 152, a drain finger 154 and a source finger 156. The gate fingers 152 are electrically connected to a common gate manifold 146, and the drain fingers 154 are electrically connected to a common drain manifold 148.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the above references in the art because this configuration is conventional in the art. (para 39 Compoche)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893