DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 20-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih [US 9,607,967] previously applied.
With respect to claim 14, Shih (fig. 5, cols. 5-9) discloses a semiconductor device, comprising:
a semiconductor die (420, col. 5, lines 44-53) including a polished surface (col. 8, lines 52-60);
an interposer (400, col. 5, lines 16-22) with the semiconductor die disposed over the interposer; and
an underfill material (430, col. 6, lines 50-58) deposited around the semiconductor die, wherein the underfill material extends to an edge of the polished surface, and wherein the polished surface inhibits progression of the underfill material onto the polished surface of the semiconductor die.
With respect to claim 20, Shih (fig. 5, cols. 5-9) discloses a semiconductor device, comprising:
a semiconductor die (420, col. 5, lines 44-53) including a polished surface (col. 8, lines 52-60); and
an underfill material (430, col. 6, lines 50-58) deposited around the semiconductor die, wherein the polished surface inhibits progression of the underfill material onto the polished surface of the semiconductor die.
With respect to claim 21, Shih (fig. 5, cols. 5-9) discloses further including an interposer (400, col. 5, lines 16-22) with the semiconductor die (420, col. 5, lines 44-53) disposed over the interposer.
With respect to claim 22, Shih (fig. 5, cols. 5-9) discloses wherein the interposer includes:
a substrate (412, col. 5, lines 23-32); and
a conductive via (416, col. 5, lines 23-32) through the substrate.
With respect to claim 23, Shih (fig. 5, cols. 5-9) discloses wherein the interposer includes:
a first insulating layer (413, col. 5, lines 22-32) formed over a first surface of the substrate; and
a first conductive layer (416a, col. 5, lines 35-53) formed over the first surface of the substrate.
With respect to claim 24, Shih (fig. 5, cols. 5-9) discloses wherein the interposer includes:
a second insulating layer (415, col. 7, lines 35-37) formed over a second surface of the second substrate opposite the first surface of the substrate;
a second conductive layer (UBM, col. 9, lines 50-52) formed over the second surface of the substrate; and
a bump (520, col. 9, lines 48-50) formed over the second conductive layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shih [US 9,607,967] previously applied, in view of Chen et al [US 2025/0105169] newly cited.
With respect to claim 15, Shih (fig. 5, cols. 5-9) discloses wherein the interposer includes:
a substrate (430, col. 6, lines 50-58); and
a conductive via (416, col. 5, lines 23-32) through the substrate.
Shih does not disclose the interposer includes semiconductor substrate. However, Chen et al disclose that it is well known in the art that the interposer (200, pp [0032]-[0033]) includes the semiconductor substrate (201, pp [0032]-[0033]). Therefore, it would have been obvious to one skill in the art to have the interposer as taught by Chen et al into the device of Shih in order to provide suitable design function for the semiconductor device.
With respect to claim 16, Shih (fig. 5, cols. 5-9) discloses wherein the interposer further includes:
a first insulating layer (413, col. 5, lines 20-32) formed over a first surface of the semiconductor substrate; and
a first conductive layer (416a, col. 5, lines 35-53) formed over the first surface of the semiconductor substrate.
With respect to claim 17, Shih (fig. 5, cols. 5-9) discloses wherein the interposer further includes:
a second insulating layer (415, col. 7, lines 35-44) formed over a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate;
a second conductive layer (UBM, col. 9, lines 45-52) formed over the second surface of the semiconductor substrate; and
a bump (520, col. 9, lines 45-52) formed over the second conductive layer.
Claims 18 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Shih [US 9,607,967] previously applied, in view of Chaware et al [US 9,385,106] previously applied.
Shih fails to disclose wherein a thickness of the semiconductor die is less than 120 micrometers. However, Chaware et al (fig. 3-3) disclose that the thickness of the semiconductor die (101, col. 7, lines 30-31) is less than 120 micrometers. Therefore, it would have been obvious to one skill in the art to have the thickness as taught by Chaware et al into the device of Shih in order to provide different device function. Moreover, the thickness range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shih [US 9,607,967] previously applied, in view of Srinivasan et al [US 2023/0086691] previously applied.
Shih fails to disclose further including a package substrate, wherein the interposer and semiconductor die are disposed over the package substrate. However, Srinivasan et al (fig. 1A) disclose the interposer (104-1, pp [0021]) and semiconductor die (114-2, 114-3, pp [0021]) are disposed over the package substrate (102, pp [0021]). Therefore, it would have been obvious to one skill in the art to have the package substrate as taught by Srinivasan et al into the device of Shih in order to complete the device structure.
Response to Arguments
Applicant's arguments filed 05/08/2026 have been fully considered but they are not persuasive.
Claim 14, Applicant argues that “Shih reference does not teach or suggest that the underfill material extends to an edge of the polished surface. The Office Action identifies the top surface of die 420 as the polished surface of claim 14 and underfill 430 as the underfill material. However, in Shih, underfill 430 is confined beneath the active face of die 420 between the die and the RDL interposer 400. Molding compound 550 surrounds the side surfaces of die 420 and is flush with the edge of the top surface of die 420, not underfill 430. Underfill 430 never reaches any edge of the top surface of die 420.”
Applicant’s argument is not persuasive because Shih (fig. 5) clearly discloses the underfill material (430, col. 6, lines 50-58) deposited around the semiconductor die, wherein the underfill material extends to an edge of the polished surface. Moreover, the claim does not recite the underfill material reaches any edge of the top surface of die. Therefore, Shih clearly meets and anticipated the claim language.
Claim 20, Applicant argues that “Shih reference does not teach or suggest that the polished surface inhibits progression of the underfill material onto the polished surface of the semiconductor die. The Office Action identifies the top surface of die 420 as the polished surface of claim 14 and underfill 430 as the underfill material. However, in Shih, underfill 430 is confined beneath the active face of die 420 between the die and the RDL interposer 400. Molding compound 550 surrounds the side surfaces of die 420, confining underfill 430. Underfill 430 never reaches any edge of the top surface of die 420, and therefore the top surface of die 420 plays no role in inhibiting underfill progression.”
Applicant’s argument is not persuasive because Shih (fig. 5) clearly discloses that the underfill material (430, col. 6, lines 50-58) deposited around the semiconductor die, wherein the polished surface inhibits progression of the underfill material onto the polished surface of the semiconductor die. Note that process limitation in claim 20 (underfill progression) do not carry weight in a claim drawn to structure. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). In addition, a “product by process” limitation is directed to the product per se, no matter how actually made, in re Hirao, 190 USPQ 15 and 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90; and In re Marosi et al., 218 USPQ 289; all of which made clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in “product by process” claims or not.
Therefore, Shih clearly meet and anticipated the claim language.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
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/HOAI V PHAM/Primary Examiner, Art Unit 2892
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