Prosecution Insights
Last updated: July 17, 2026
Application No. 18/483,657

FIELD EFFECT TRANSISTOR WITH ALIGNMENT MARK AND RELATED METHODS

Non-Final OA §103§112
Filed
Oct 10, 2023
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
50%
Grant Probability
Moderate
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
2 granted / 4 resolved
-18.0% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
41 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
93.1%
+53.1% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 4 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 31 March 2026 is acknowledged. Claims 8-13 have been cancelled and claims 21-26 added. Claim Objections Claims 15-20 are objected to because of the following informalities: These claims contain instances of “the forming” where only the word “forming” is appropriate. For the purpose of examination, only the word “forming” will be used in these instances. Appropriate correction is required. Claims 15 is objected to because of the following informalities: These claims contain instances of “the recessing” where only the word “recessing” is appropriate. For the purpose of examination, only the word “recessing” will be used in these instances. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim 20 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. The phrase ”...forming a plurality of alignment implants during forming first wells...”. For the purpose of examination, --a plurality of alignment implants-- will be replaced by --an alignment implant--. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 7, 14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dietz et al (US 20070048959 A1, hereinafter “Dietz”), in view of Park et al (US 20240128354 A1, hereinafter “Park”). Regarding Claim 1 - Dietz discloses a method, comprising: forming a first mask over a substrate (considered as 505 [0014] and Fig. 5); forming first openings and a second opening in the first mask (510a and 510b [0014] and Fig. 5); forming first wells in first regions of the substrate exposed by the first openings (515 [0014] in area 255 [0011] and Fig. 5) and an alignment implant in a second region of the substrate exposed by the second opening (515 [0014] in area 222 [0011] and Fig. 5); forming an alignment mark by recessing the alignment implant (605 [0017] and Fig. 5). Dietz fails to disclose patterning a multi-layer semiconductor lattice under alignment of the alignment mark. However, Park discloses patterning a multi-layer semiconductor lattice under alignment of the alignment mark (Park [0146], [0148], and [0150] and Figs. 51, 52, and 55). Park discloses a similar etched alignment mark to Dietz. Park teaches patterning a multilayer semiconductor lattice for the benefit of forming active regions of nanosheet transistors (405, Park [0150] and Fig. 52, shown as 422 in Park Fig. 51. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Park to pattern a multilayer semiconductor lattice using the alignment mark for the benefit of forming active regions of nanosheet transistors. PNG media_image1.png 378 540 media_image1.png Greyscale PNG media_image2.png 448 759 media_image2.png Greyscale PNG media_image3.png 423 472 media_image3.png Greyscale PNG media_image4.png 490 773 media_image4.png Greyscale Regarding Claim 2 - Dietz modified by Park discloses all the limitations of claim 1. The combination of Dietz and Park further discloses forming a second mask over the substrate (considered as 805, Dietz [0020] and Fig. 8); forming third openings in the second mask (805a and 805b in annotated Dietz Fig. 8); and forming second wells in third regions of the substrate exposed by the third openings (810, Dietz [0020] and Fig. 8), the second wells being of different type than the first wells (515 are p-type, boron-doped [0014] and 810 are n-type, for example phosphorous-doped [0020]). PNG media_image5.png 276 542 media_image5.png Greyscale Regarding Claim 3 - Dietz modified by Park discloses all the limitations of claim 2. The combination of Dietz and Park further discloses forming first wells includes forming P-type wells (515 [0014]). Regarding Claim 4 - Dietz modified by Park discloses all the limitations of claim 2. The combination of Dietz and Park fails to expressly disclose forming a second mask includes: forming a first mask layer on the substrate, the first mask layer extending into a recess over the alignment mark; and forming a second mask layer over the first mask layer. However, Dietz discloses forming the first mask layer (505, Dietz [0014] and Fig. 5) includes: forming a previous mask layer on the substrate (130, Dietz [0012] and Fig. 5), the previous mask layer extending into a recess over the alignment mark (510b, Dietz [0014] and Fig. 5); and forming a first mask layer over the previous mask layer (505 over 130, Dietz [0014] and Fig. 5). Leaving the previous mask when applying the first mask saves process steps while ensuring alignment of layers using 510b, as shown in Dietz Fig. 5. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider following the teaching of Dietz to form a second mask over a first mask layer that extends into a recess over the alignment mark for the benefit of saving process steps while ensuring alignment between layers. Regarding Claim 5 - Dietz modified by Park discloses all the limitations of claim 1. The combination of Dietz and Park further discloses depositing a semiconductor material layer in a third opening over the alignment mark (first layer of 410/411, Park [0148] and Fig. 55); and forming the multi-layer semiconductor lattice by depositing alternating first semiconductor layers and second semiconductor layers on the semiconductor material layer and the substrate (410/411 and 420/421, Park [0148] and Fig. 55). Regarding Claim 7 - Dietz modified by Park discloses all the limitations of claim 2. The combination of Dietz and Park further discloses recessing the alignment implant is etching the alignment implant partially such that vertical sidewalls of the alignment implant remain in the alignment mark (as shown in Dietz Fig. 8). Regarding Claim 14 - Dietz discloses a method, comprising: in a same implantation operation, forming first wells in first regions of a substrate and an alignment implant in a second region of the substrate offset from the first regions (210 in 255, and 210 and 515 in 222, Dietz [0011] and Figs. 2 and 5); forming an alignment mark by recessing the alignment implant in a self-aligned process while the first wells are masked (605, Dietz [0017] and Fig. 6). Dietz fails to disclose patterning a multi-layer semiconductor lattice under alignment of the alignment mark. However, Park discloses patterning a multi-layer semiconductor lattice under alignment of the alignment mark (Park [0146], [0148], and [0150] and Figs. 51, 52, and 55). Park discloses a similar etched alignment mark to Dietz. Park teaches patterning a multilayer semiconductor lattice for the benefit of forming active regions of nanosheet transistors (405, Park [0150] and Fig. 52, shown as 422 in Park Fig. 51. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Park to pattern a multilayer semiconductor lattice using the alignment mark for the benefit of forming active regions of nanosheet transistors. PNG media_image6.png 347 577 media_image6.png Greyscale PNG media_image7.png 334 549 media_image7.png Greyscale Regarding Claim 18 - Dietz modified by Park discloses all the limitations of claim 14. The combination of Dietz and Park further discloses forming first wells includes forming the first wells having width in a first direction that does not exceed width of the alignment implant in the first direction (Width of 210 in 255 less than width of combination of 520 [0016] and 515 in 222, Dietz Fig. 5). Regarding Claim 19 - Dietz modified by Park discloses all the limitations of claim 18. The combination of Dietz and Park further discloses forming an alignment implant includes forming the alignment implant having length in a second direction that does not exceed length of the first wells in the second direction, the second direction being transverse the first direction (Width of alignment mark area 419 in D2 less than width in direction D1, Park Fig. 51). Park discloses a similar etched alignment mark to Dietz. Park teaches making the width of the alignment mark in the direction D2 less than in the direction D1 for the benefit of placing an alignment adjacent to each active area (Park Fig. 51). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Park to make the width of the alignment mark in the direction D2 less than in the direction D1 for the benefit of placing an alignment adjacent to each active area. Regarding Claim 20 - Dietz modified by Park discloses all the limitations of claim 19. The combination of Dietz and Park further discloses forming an alignment implant during forming first wells (210, Dietz [0011] and Fig. 3 in multiple locations as in 419 of Park [0148] and Fig. 51), the alignment implants being arranged along the second direction (Maximum length of 422 between isolation regions 430 in direction D2, Park Fig. 51), a total length of the plurality of alignment implants not exceeding the length of the first wells (419 length in D2 is less than 422, Park Fig. 51). Claims 6, 21-22, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Dietz et al (US 20070048959 A1, hereinafter “Dietz”), in view of Park et al (US 20240128354 A1, hereinafter “Park”), and further in view of Chang et al (US 20150206873 A1, hereinafter “Chang”). Regarding Claim 6 - Dietz modified by Park discloses all the limitations of claim 1. The combination of Dietz and Park fails to disclose recessing the alignment implant is etching the alignment implant partially without breaking through the alignment implant. However, Chang discloses recessing the alignment implant is etching the alignment implant partially without breaking through the alignment implant (36, Chang [0019] and Fig. 4). Chang discloses a semiconductor device with implanted wells and etched alignment marks similar to Dietz. Chang teaches recessing the alignment marks without breaking through the alignment implant allows the desired topography to be transferred into the substrate without excessively high depth (Chang [0019]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Chang to recess the alignment marks without breaking through the alignment implant for the benefit of allowing the desired topography to be transferred into the substrate without excessively high depth. PNG media_image8.png 223 732 media_image8.png Greyscale Regarding Claim 21 - Dietz discloses a method, comprising: forming a first mask structure over a substrate (considered as 205 [0011] and Fig. 3); forming a first opening with a first width (305 in 255 in Fig. 3) and a second opening in the first mask structure with a second width greater than or equal to the first width (305 openings shown with equal width in 222 in Fig. 3); forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening (210 in 255 and 222, Dietz [0011] and Fig. 2); forming a second mask structure over the substrate and filling the first opening (505 covering 305 in 255 in Fig. 5); forming an alignment mark by forming a recess in the alignment implant exposed by the second opening (605 [0017] and Fig. 6). Dietz fails to disclose patterning a multi-layer semiconductor lattice under alignment of the alignment mark. However, Park discloses patterning a multi-layer semiconductor lattice under alignment of the alignment mark (Park [0146], [0148], and [0150] and Figs. 51, 52, and 55). Park discloses a similar etched alignment mark to Dietz. Park teaches patterning a multilayer semiconductor lattice for the benefit of forming active regions of nanosheet transistors (405, Park [0150] and Fig. 52, shown as 422 in Park Fig. 51. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Park to pattern a multilayer semiconductor lattice using the alignment mark for the benefit of forming active regions of nanosheet transistors. The combination of Dietz and Park fails to disclose the recess has a first depth and the alignment implant has a second depth greater than the first depth; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark. However, Chang discloses the recess has a first depth and the alignment implant has a second depth greater than the first depth (28 deeper than 36, Chang [0019] and Fig. 4). Chang discloses a semiconductor device with implanted wells and etched alignment marks similar to Dietz. Chang teaches recessing the alignment marks without breaking through the alignment implant allows the desired topography to be transferred into the substrate without excessively high depth (Chang [0019]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Chang to recess the alignment marks without breaking through the alignment implant for the benefit of allowing the desired topography to be transferred into the substrate without excessively high depth. Regarding Claim 22 - Dietz modified by Park and Chang discloses all the limitations of claim 21. The combination of Dietz, Park, and Chang further discloses forming the second mask further includes leaving the second opening empty (Dietz Fig. 5 shows the second opening, 510, empty in area 222). Regarding Claim 24 - Dietz modified by Park and Chang discloses all the limitations of claim 21. The combination of Dietz, Park, and Chang further discloses the recess has the second width (605, Dietz [0017] and Fig. 6). Regarding Claim 25 - Dietz modified by Park and Chang discloses all the limitations of claim 24. The combination of Dietz, Park, and Chang further discloses the alignment implant has a third width greater than the second width (515 wider than 510b in Dietz Fig. 5 and 305 in Dietz Fig. 2). Regarding Claim 26 - Dietz modified by Park and Chang discloses all the limitations of claim 24. The combination of Dietz, Park, and Chang further discloses forming a third mask structure to fill the recess in the alignment implant (805, Dietz [0020] and Fig. 8). Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dietz et al (US 20070048959 A1, hereinafter “Dietz”), in view of Park et al (US 20240128354 A1, hereinafter “Park”), and further in view of Huang et al (US 20190148145 A1, hereinafter “Huang”). Regarding Claim 15 - Dietz modified by Park discloses all the limitations of claim 14. The combination of Dietz and Park further discloses forming a bottom mask layer on the substrate (The combination of 130 and 125 can be considered a bottom mask layer, Dietz [0014] and Fig. 6); forming an alignment implant and recessing the alignment implant are performed through a same opening in the bottom mask layer (210, 515, and 605, Dietz [0011], [0014] and [0017] and Fig. 6). The combination of Dietz and Park fails to disclose forming a middle mask layer on the bottom mask layer; and forming a photosensitive layer on the middle mask layer. However, Huang discloses forming a middle mask layer on the bottom mask layer (208 over 206, Huang [0020] and Fig. 2A); and forming a photosensitive layer on the middle mask layer (210 over 208, Huang [0020] and Fig. 2A). Huang discloses a patterning scheme compatible with Dietz. Huang teaches using middle and bottom layers with a photosensitive layer for the benefit of controlling feature size with decreasing size and pitch (Huang [0001-0002]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Huang to use middle and bottom layers with a photosensitive layer for the benefit of controlling feature size with decreasing size and pitch. PNG media_image9.png 259 420 media_image9.png Greyscale Regarding Claim 16 - Dietz modified by Park and Huang discloses all the limitations of claim 15. The combination of Dietz, Park, and Huang further discloses removing the bottom mask layer (Dietz [0018]); and forming second wells of a different dopant type than the first wells (515 are p-type, boron-doped [0014] and 210 are n-type, for example phosphorous-doped [0011]). The combination of Dietz, Park, and Huang fails to disclose forming a second bottom mask layer, the second bottom mask layer covering the alignment mark, forming second wells being through openings in the second bottom mask layer. However, forming a second mask stack with a bottom layer as in the first mask layer stack with a bottom layer represents duplication of parts, and a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Regarding Claim 17 - Dietz modified by Park and Huang discloses all the limitations of claim 15. The combination of Dietz, Park, and Huang further discloses after forming an alignment implant: forming a second photosensitive layer covering the first wells (505, Dietz [0014] and Fig. 5) and exposing the same opening through which the alignment implant is recessed (305 in Fig. 3 and 510b in Dietz Fig. 5). Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Dietz et al (US 20070048959 A1, hereinafter “Dietz”), in view of Park et al (US 20240128354 A1, hereinafter “Park”), and further in view of Chang et al (US 20150206873 A1, hereinafter “Chang”), and further in view of Huang et al (US 20190148145 A1, hereinafter “Huang”). Regarding Claim 23 - Dietz modified by Park and Chang discloses all the limitations of claim 21. The combination of Dietz, Park, and Chang fails to disclose forming the first mask structure further includes: forming a bottom mask layer on the substrate (The combination of 130 and 125 can be considered a bottom mask layer, Dietz [0014] and Fig. 6). The combination of Dietz and Park fails to disclose forming a middle mask layer on the bottom mask layer; and forming a photosensitive layer on the middle mask layer. However, Huang discloses forming a middle mask layer on the bottom mask layer (208 over 206, Huang [0020] and Fig. 2A); and forming a photosensitive layer on the middle mask layer (210 over 208, Huang [0020] and Fig. 2A). Huang discloses a patterning scheme compatible with Dietz. Huang teaches using middle and bottom layers with a photosensitive layer for the benefit of controlling feature size with decreasing size and pitch (Huang [0001-0002]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Dietz and Huang to use middle and bottom layers with a photosensitive layer for the benefit of controlling feature size with decreasing size and pitch. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571)272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Oct 10, 2023
Application Filed
Nov 22, 2023
Response after Non-Final Action
May 26, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
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Prosecution Projections

1-2
Expected OA Rounds
50%
Grant Probability
99%
With Interview (+100.0%)
3y 3m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 4 resolved cases by this examiner. Grant probability derived from career allowance rate.

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