Office Action Predictor
Application No. 18/483,695

EMBEDDING A METAL-INSULATOR-METAL CAPACITOR IN A PASSIVATION LAYER

Non-Final OA §102
Filed
Oct 10, 2023
Examiner
FOX, BRANDON C
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, LTD.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

86%
Career Allow Rate
684 granted / 798 resolved
Without
With
+10.0%
Interview Lift
avg trend
2y 5m
Avg Prosecution
26 pending
824
Total Applications
career history

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
33.9%
-6.1% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a Non-Final office action based on application 18/483,695 filed October 10, 2023. Claims 1-20 are currently pending and have been considered below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7-9, 12, & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu (Pre-Grant Publication 2019/0035674). Regarding claim 1, Chiu discloses a device comprising: an interconnect structure (Fig. 1, 11/11c); a first passivation layer disposed over the interconnect structure; a recess (TR1) disposed within the first passivation layer; a first conductive layer (31p) disposed over the interconnect structure and partially within the recess; an insulator layer (32p) disposed over the first conductive layer and partially within the recess; a second conductive layer (33p) disposed over the insulator layer, wherein the second conductive layer completely fills the recess; and a second passivation layer (50) disposed over the second conductive layer. Regarding claim 7, Chiu further discloses: the first conductive layer and the second conductive layer contain titanium nitride; and the insulator layer contains hafnium oxide or zirconium oxide (Paragraph [0023]). Regarding claim 8, Chiu discloses a device comprising: a first passivation layer (Fig. 1, 22) disposed over an interconnect structure (11/11c); a second passivation layer (50) disposed over the first passivation layer; and a metal-insulator-metal (MIM) capacitor (C1) disposed between the first passivation layer and the second passivation layer, wherein the MIM capacitor includes a downward protruding portion that protrudes at least partially through the first passivation layer. Regarding claim 9, Chiu further discloses: the MIM capacitor includes a first conductive layer (31p), an insulator layer (32p) disposed over the first conductive layer, and a second conductive layer (33p) over the insulator layer; and the second conductive layer includes a further downwardly protruding portion that is in direct contact with side surfaces of the insulator layer and the first conductive layer (Fig. 1). Regarding claim 12, Chiu discloses a method comprising: forming a passivation layer (Figs. 2-9, 22) over an interconnect structure (11/11c); etching an opening (TR1) at least partially through the passivation layer; depositing a first conductive layer (31) over the passivation layer, wherein the first conductive layer partially fills the opening; depositing an insulator layer (32) over the first conductive layer, wherein the insulator layer partially fills the opening; depositing a second conductive layer (33) over the insulator layer, wherein the second conductive layer completely fills the opening; and forming a first conductive structure (S1) that is electrically coupled to the first conductive layer and forming a second conductive structure (S2) that is electrically coupled to the second conductive layer. Regarding claim 20, Chiu further discloses: the first conductive layer, the insulator layer, and the second conductive layer collectively form a first metal-insulator-metal (MIM) capacitor structure (C1), and wherein the method further comprises forming a second MIM capacitor structure (C2) over the first MIM capacitor structure. Allowable Subject Matter Claims 2-6, 10-11, & 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 2 is considered allowable because none of the prior art either alone or in combination discloses the second passivation layer and the first passivation layer have different material compositions. Claim 3 is considered allowable because none of the prior art either alone or in combination discloses a first conductive via that extends through the second passivation layer, the second conductive layer, the insulator layer, the first conductive layer, and the first passivation layer, wherein the first conductive via is electrically coupled to the first conductive layer disposed in the recess but not to the second conductive layer disposed in the recess; and a second conductive via that extends through the second passivation layer, the second conductive layer, the insulator layer, the first conductive layer, and the first passivation layer, wherein the second conductive via is electrically coupled to the second conductive layer disposed in the recess but not to the first conductive layer disposed in the recess. Claim 4 is also allowable based on its dependency from claim 3. Claim 5 is considered allowable because none of the prior art either alone or in combination discloses the first conductive layer, the insulator layer, and the second conductive layer collectively form a first metal-insulator-metal (MIM) capacitor, and wherein the device further comprises a second MIM capacitor disposed at least partially over the second passivation layer. Claim 6 is also allowable based on its dependency from claim 5. Claim 10 is considered allowable because none of the prior art either alone or in combination discloses the MIM capacitor is a first MIM capacitor; the device further comprises a second MIM capacitor disposed over the first MIM capacitor; and the second MIM capacitor lacks a downwardly protruding portion. Claim 11 is also allowable based on its dependency from claim 10. Claim 13 is considered allowable because none of the prior art either alone or in combination discloses the opening is etched partially, but not completely, through the passivation layer. Claim 14 is considered allowable because none of the prior art either alone or in combination discloses the passivation layer is a first passivation layer, wherein the opening is a first opening, and wherein the method further comprises, after the second conductive layer has been deposited: etching a second opening through a segment of the second conductive layer outside the first opening but not through the insulator layer and the first conductive layer; and forming a second passivation layer over the second conductive layer, wherein the second passivation layer fills the second opening. Claims 15 & 16 are also allowable based on their dependency from claim 14. Claim 17 is considered allowable because none of the prior art either alone or in combination discloses the opening is a first opening, and wherein the method further comprises, after the first conductive layer has been deposited but before the insulator layer has been deposited, etching a second opening through a segment of the first conductive layer outside the first opening, wherein the depositing of the insulator layer and the depositing of the second conductive layer fill the second opening. Claims 18 & 19 are also allowable based on their dependency from claim 17. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRANDON C FOX/Examiner, Art Unit 2818 /DAVID VU/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Oct 10, 2023
Application Filed
Dec 22, 2025
Non-Final Rejection — §102
Mar 31, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+10.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 798 resolved cases by this examiner