CTNF 18/483,739 CTNF 100838 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Invention I in the reply filed on 10 April 2026 is acknowledged. 08-06 AIA Claim s 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10 April 2026 . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the differences between first and second widths in claims 9 and 18 must be shown or the features canceled from the claims. No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections 07-29-01 AIA Claim 11 is objected to because of the following informalities: The claim contains the limitation --a first conductor structure disposed on the a backside of the substrate--. For the purpose of examination, the word --the-- will be ignored . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-36 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. 07-36-01 Claim 22 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 22 fails to further limit the subject matter of claim 21. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3, 5, 7-8, 11, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sinha et al (US 20240107738 A1, hereinafter “Sinha”), in view of Chao et al (US 20150348962 A1, hereinafter “Chao”) . Regarding Claim 1 - Sinha discloses a memory device, comprising: a substrate having a first side and a second side opposite to each other (102 [0080] and Fig. 6); a plurality of memory cells formed on the first side of the substrate ([0130]); Sinha fails to disclose a header device formed on the first side of the substrate; wherein the header device is configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal. However, Chao discloses a header device formed on the first side of the substrate (130α or 130β [0043] and Fig. 5); wherein the header device is configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal (190α and 190β in Fig. 5). Chao discloses a circuit compatible with Sinha. Chao teaches configuring header devices (power gating cells or PGC) to control the distribution of power in circuits for the benefits of reduced leakage and power consumption (Chao [0016]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sinha and Chao to configure a header device to control the power distribution in a circuit for the benefits of reduced leakage and power consumption. PNG media_image1.png 551 634 media_image1.png Greyscale PNG media_image2.png 625 541 media_image2.png Greyscale Regarding Claim 2 - Sinha modified by Chao discloses all the limitations of claim 1. The combination of Sinha and Chao further discloses a first conductor structure disposed on the second side of the substrate and configured to provide the supply voltage (3202 Sinha [0156] and Fig. 35); a plurality of second via structures disposed on the second side of the substrate and configured to electrically couple the first conductor structure to the memory cells, respectively (3322 Sinha [0157] and Fig. 35); a second conductor structure disposed on the first side of the substrate and configured to deliver the supply voltage to the memory cells (3203 Sinha [0155] and Fig. 35); and a plurality of fourth via structures disposed on the first side of the substrate and configured to electrically couple the second conductor structure to the memory cells, respectively (3312 Sinha [0155] and Fig. 35). Sinha fails to expressly disclose a first via structure disposed on the second side of the substrate and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device; a third via structure disposed on the first side of the substrate and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure. However, given the combination of backside and frontside conductor and via structures of Sinha with the header device of Chao, a first via structure disposed on the second side of the substrate and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device, and a third via structure disposed on the first side of the substrate and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure are both examples of a duplication of parts and present a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Connecting a power supply to one source/drain of the header device using backside conductor and via structures, and using frontside conductor and via structures to connect the memory devices to the other source/drain of the header device are simply examples of applying the existing circuit components of Sinha to the added header device of Chao. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a via structure on the second side of the substrate to connect the first conductor structure to a first source/drain terminal of the header device, and a via structure on the first side of the substrate to connect the second conductor structure to the second source/drain terminal of the header device. PNG media_image3.png 486 705 media_image3.png Greyscale Regarding Claim 3 - Sinha modified by Chao discloses all the limitations of claim 2. The combination of Sinha and Chao further discloses the first combination of power delivery paths include: a first path extending from the first conductor structure, through one of the second via structures, and to one of the memory cells (3202 to 3322 to 3210, Sinha [0156] and Fig. 35). Neither Sinha nor Chao individually discloses a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells. However, given the combination of backside and frontside conductor and via structures of Sinha with the header device of Chao, a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells is an example of a duplication of parts (specifically the via structures to connect the header device, and the header device as a PMOS or NMOS transistor), and presents a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Connecting a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells is an example of applying the existing circuit components of Sinha to the added header device of Chao. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a via structure on the second side of the substrate to connect a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells. Regarding Claim 5 - Sinha modified by Chao discloses all the limitations of claim 2. The combination of Sinha and Chao further discloses the second combination of power delivery paths include: a path extending from the first conductor structure, through one of the second via structures, and to one of the memory cells (3203 to upper transistors, Sinha [0153] and Fig. 35). Regarding Claim 7 - Sinha modified by Chao discloses all the limitations of claim 1. The combination of Sinha and Chao further discloses the supply voltage is VDD or VSS (Sinha [0153]). Regarding Claim 8 - Sinha modified by Chao discloses all the limitations of claim 2. The combination of Sinha and Chao further discloses the first via structure has a first width extending along a first direction perpendicular to a second direction along which the first conductor structure extends, and the second via structures, the third via structures, and the fourth via structures have a second width extending along the first direction (Vias have first and second widths, Y and X, annotated Sinha Fig. 35). Regarding Claim 11 - Sinha discloses a memory device, comprising: a plurality of memory cells formed on a frontside of a substrate (102 [0080], [0130], and Fig. 6); a first conductor structure disposed on a backside of the substrate and configured to provide a supply voltage; a plurality of second via structures disposed on the backside and configured to electrically couple the first conductor structure to the memory cells, respectively (3322 Sinha [0157] and Fig. 35); a second conductor structure disposed on the frontside and configured to deliver the supply voltage to the memory cells (3203 Sinha [0155] and Fig. 35); and a plurality of fourth via structures disposed on the frontside and configured to electrically couple the second conductor structure to the memory cells, respectively (3312 Sinha [0155] and Fig. 35). Sinha fails to disclose a header device also formed on the front side; a first via structure disposed on the backside and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device; a third via structure disposed on the frontside and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure; However, Chao discloses a header device formed on the first side of the substrate (130α or 130β [0043] and Fig. 5). Chao discloses a circuit compatible with Sinha. Chao teaches using header devices (power gating cells or PGC) to control the distribution of power in circuits for the benefits of reduced leakage and power consumption (Chao [0016]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sinha and Chao to use a header device to control the power distribution in a circuit for the benefits of reduced leakage and power consumption. Further, given the combination of backside and frontside conductor and via structures of Sinha with the header device of Chao, a first via structure disposed on the second side of the substrate and configured to electrically couple the first conductor structure to a first source/drain terminal of the header device, and a third via structure disposed on the first side of the substrate and configured to electrically couple a second source/drain terminal of the header device to the second conductor structure are both examples of a duplication of parts and present a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Connecting a power supply to one source/drain of the header device using backside conductor and via structures, and using frontside conductor and via structures to connect the memory devices to the other source/drain of the header device are simply examples of applying the existing circuit components of Sinha to the added header device of Chao. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a via structure on the second side of the substrate to connect the first conductor structure to a first source/drain terminal of the header device, and a via structure on the first side of the substrate to connect the second conductor structure to the second source/drain terminal of the header device. Regarding Claim 16 - Sinha modified by Chao discloses all the limitations of claim 11. The combination of Sinha and Chao further discloses the header device has p-type conductivity and the supply voltage is VDD (110 Chao [00160 and Fig. 1A). PNG media_image4.png 297 144 media_image4.png Greyscale Regarding Claim 17 - Sinha modified by Chao discloses all the limitations of claim 11. The combination of Sinha and Chao further discloses the header device has n-type conductivity and the supply voltage is VSS (160 Chao [0026] and Fig. 2) . PNG media_image5.png 276 127 media_image5.png Greyscale 07-21-aia AIA Claim s 10, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Sinha et al (US 20240107738 A1, hereinafter “Sinha”), in view of Chao et al (US 20150348962 A1, hereinafter “Chao”), and further in view of Lu et al (US 7,292,485 B1, hereinafter “Lu”) . Regarding Claim 10 - Sinha modified by Chao discloses all the limitations of claim 1. Sinha modified by Chao fails to expressly disclose when the control signal is provided at a first logic state, the header device is configured to couple the supply voltage through the first combination of power delivery paths to one or more of the memory cells, and when the control signal is provided at a second logic state, the header device is configured to couple the supply voltage through the second combination of power delivery paths to one or more of the memory cells. However, Lu discloses when the control signal is provided at a first logic state, the header device is configured to couple the supply voltage through the first combination of power delivery paths to one or more of the memory cells (e.g. Clamping circuit 46, Lu column 3, lines 29-58, and Fig. 2), and when the control signal is provided at a second logic state, the header device is configured to couple the supply voltage through the second combination of power delivery paths to one or more of the memory cells (e.g. Clamping circuit 46 and P-channel header transistor 52, Lu column 3, lines 29-58, and Fig. 2). Lu discloses an SRAM circuit analogous to Sinha. Lu teaches using one or both power supply paths to the SRAM circuit for the benefits of writing data more easily and improving cell stability (Lu column 2, lines 6-23). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to the claimed invention that both or only the clamping circuit could be used to power the SRAM cells for the benefits of writing data more easily and improving cell stability. Regarding Claim 21 - Sinha discloses a memory device, comprising: a substrate having a first side and a second side opposite to each other (102 [0080] and Fig. 6); a plurality of memory cells formed on the first side of the substrate ([0130]). Sinha fails to disclose a header device formed on the first side of the substrate; wherein when the header device is turned on, a supply voltage is delivered to the plurality of memory cells through a first path and a second path, and wherein when the header device is turned off, the supply voltage is delivered to the plurality of memory cells through a single path. However, Chao discloses a header device formed on the first side of the substrate (130 [0016] and Fig. 1B). Chao discloses a circuit compatible with Sinha. Chao teaches using header devices (power gating cells or PGC) to control the distribution of power in circuits for the benefits of reduced leakage and power consumption (Chao [0016]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sinha and Chao to use a header device to control the power distribution in a circuit for the benefits of reduced leakage and power consumption. In addition, the operation of the device does not differentiate over the prior art, and is not patentable. See MPEP 2114(II). However, Lu discloses the structure of two parallel paths for supply voltage in SRAM cells (Clamping circuit 46 and P-channel header transistor 52, Lu column 3, lines 29-58, and Fig. 2). Lu discloses an SRAM circuit analogous to Sinha. Lu teaches using one or both power supply paths to the SRAM circuit for the benefits of writing data more easily and improving cell stability (Lu column 2, lines 6-23). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to the claimed invention that both or only the clamping circuit could be used to power the SRAM cells for the benefits of writing data more easily and improving cell stability. PNG media_image6.png 592 799 media_image6.png Greyscale Regarding Claim 22 - Sinha modified by Chao and Lu discloses all the limitations of claim 21. The combination of Sinha, Chao, and Lu further discloses the header device is configured to selectively couple the supply voltage through the first path and the second path (P-channel header transistor 52, Lu column 3, lines 29-58, and Fig. 2), or the single path to the plurality of memory cells based on a control signal (Clamping circuit 46, Lu column 3, lines 29-58, and Fig. 2) . 07-21-aia AIA Claim s 4,6, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sinha et al (US 20240107738 A1, hereinafter “Sinha”), in view of Chao et al (US 20150348962 A1, hereinafter “Chao”), and further in view of MPEP 2114(II) . Regarding Claim 4 - Sinha modified by Chao discloses all the limitations of claim 3. The combination of Sinha and Chao appears to be silent regarding whether the header device is turned on. This claim relates to the operation of the device rather than the structure of the device, and is therefore unpatentable over the prior art. See MPEP 2114(II). However, the structure exists in the combination of Sinha and Chao to support this mode of operation. Given the configuration of the combination of Sinha and Chao, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the header device could be turned on. Regarding Claim 6 - Sinha modified by Chao discloses all the limitations of claim 5. The combination of Sinha and Chao appears to be silent regarding whether the header device is turned off. This claim relates to the operation of the device rather than the structure of the device, and is therefore unpatentable over the prior art. See MPEP 2114(II). However, the structure exists in the combination of Sinha and Chao to support this mode of operation. Given the configuration of the combination of Sinha and Chao, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the header device could be turned on. Regarding Claim 12 - Sinha modified by Chao discloses all the limitations of claim 11. The combination of Sinha and Chao appears to be silent regarding when the header device is turned on, the supply voltage is delivered to one or more of the memory cells through a first path and a second path. This claim relates to the operation of the device rather than the structure of the device, and is therefore unpatentable over the prior art. See MPEP 2114(II). However, the structure exists in the combination of Sinha and Chao to support this mode of operation. Given the configuration of the combination of Sinha and Chao, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the supply voltage could be delivered to one or more of the memory cells through a first path and a second path. Regarding Claim 13 - Sinha modified by Chao in view of MPEP 2114(II) discloses all the limitations of claim 12. The combination of Sinha and Chao further discloses the first path extends from the first conductor structure, through respective ones of the second via structures, and to the one or more memory cells (3202 to 3322 to 3210, Sinha [0156] and Fig. 35), and the second path extends through the header device to the one or more memory cells (through header device 130 to circuit 150, Chao [0043] and Fig. 5). Neither Sinha nor Chao individually discloses the second path extends from the first conductor structure, through the first via structure, the header device, the third via structure, the second conductor structure, and respective ones of the fourth via structures, and to the one or more memory cells. However, given the combination of backside and frontside conductor and via structures of Sinha with the header device of Chao, a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells is an example of a duplication of parts (specifically the via structures to connect the header device, and the header device as a PMOS or NMOS transistor), and presents a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Connecting a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells is an example of applying the existing circuit components of Sinha to the added header device of Chao. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a via structure on the second side of the substrate to connect a second path extending from the first conductor structure, through the first via structure, the header device, the third via structure, and one of the fourth via structures, and to one of the memory cells. Regarding Claim 14 - Sinha modified by Chao discloses all the limitations of claim 11. The combination of Sinha and Chao appears to be silent regarding when the header device is turned off, the supply voltage is delivered to one or more of the memory cells through a single path. This claim relates to the operation of the device rather than the structure of the device, and is therefore unpatentable over the prior art. See MPEP 2114(II). However, the structure exists in the combination of Sinha and Chao to support this mode of operation. Given the configuration of the combination of Sinha and Chao, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the supply voltage could be delivered to one or more of the memory cells through a single path. Regarding Claim 15 - Sinha modified by Chao in view of MPEP 2114(II) discloses all the limitations of claim 14. The combination of Sinha and Chao further discloses the single path extends from the first conductor structure, through respective ones of the second via structures, and to the one or more memory cells (3202 to 3322 to 3210, Sinha [0156] and Fig. 35) . 07-21-aia AIA Claim s 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sinha et al (US 20240107738 A1, hereinafter “Sinha”), in view of Chao et al (US 20150348962 A1, hereinafter “Chao”), and further in view Narayan et al (US 20230299068 A1, hereinafter “Narayan”) . Regarding Claim 9 - Sinha modified by Chao discloses all the limitations of claim 8. The combination of Sinha and Chao fails to disclose the first width is substantially greater than the second width. However, Narayan discloses the first width is substantially greater than the second width (Narayan Fig. 3). Narayan discloses an analogous MOSFET cell structure to Sinha. Narayan teaches the first width is greater than the second width for the advantage of improving area utilization within the cell layout (Narayan [0041]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Sinha and Narayan to make the first width is greater than the second width for the advantage of improving area utilization within the cell layout. Regarding Claim 18 - Sinha modified by Chao discloses all the limitations of claim 11. The combination of Sinha and Chao further discloses the first conductor structure and the second conductor structure each extend along a first direction (Parallel with X in Sinha annotated Fig. 35), the first via structure has a first width extending along a second direction perpendicular to the first direction, each of the second via structures, the third via structure, and the fourth via structures have a second width extending along the second direction (The vias have first and second widths, Y and X, annotated Sinha Fig. 35). The combination of Sinha and Chao fails to disclose the first width is substantially greater than the second width. However, Narayan discloses the first width is substantially greater than the second width (Narayan Fig. 3). Narayan discloses an analogous MOSFET cell structure to Sinha. Narayan teaches the first width is greater than the second width for the advantage of improving area utilization within the cell layout (Narayan [0041]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Sinha and Narayan to make the first width is greater than the second width for the advantage of improving area utilization within the cell layout. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/483,739 Page 2 Art Unit: 2898 Application/Control Number: 18/483,739 Page 3 Art Unit: 2898 Application/Control Number: 18/483,739 Page 4 Art Unit: 2898 Application/Control Number: 18/483,739 Page 5 Art Unit: 2898 Application/Control Number: 18/483,739 Page 6 Art Unit: 2898 Application/Control Number: 18/483,739 Page 7 Art Unit: 2898 Application/Control Number: 18/483,739 Page 8 Art Unit: 2898 Application/Control Number: 18/483,739 Page 9 Art Unit: 2898 Application/Control Number: 18/483,739 Page 10 Art Unit: 2898 Application/Control Number: 18/483,739 Page 11 Art Unit: 2898 Application/Control Number: 18/483,739 Page 12 Art Unit: 2898 Application/Control Number: 18/483,739 Page 13 Art Unit: 2898 Application/Control Number: 18/483,739 Page 14 Art Unit: 2898 Application/Control Number: 18/483,739 Page 15 Art Unit: 2898
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