DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Lee, US 2022/0165721).
Regarding claim 1, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising: a substrate (substrate 20 and [0029]); a composite interposer (C2 in FIG. 2) disposed over the substrate (substrate 20) and comprising: a first interposer substrate (PDC in FIG. 3) comprising a first conductive via (BP2) and a first dielectric layer (IMD3); and a second interposer substrate (PDN) disposed over the first interposer substrate (PDC) and comprising a second conductive via (BP1) and a second dielectric layer (IMD2), wherein the second conductive via is bonded to the first conductive via ( see interface of BP1 And BP2), and the second dielectric layer is bonded to the first dielectric layer (interface IMD3 and IMD2); and a semiconductor die (IC die in FIG. 3) disposed over the composite interposer and electrically coupled to the first conductive via (BP1) and the second conductive via (BP2).
Regarding claim 2, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising wherein a first top surface area of the first conductive via (BP1) is greater than a first bottom surface area of the first conductive via (see BP1 FIG. 3), and a second bottom surface area of the second conductive via is greater than a second top surface area of the second conductive via (see FIG. 3).
Regarding claim 3, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising wherein the second bottom surface area of the second conductive via (BP2) is substantially equal to the first top surface area of the first conductive via (BP1).
Regarding claim 4, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising wherein the composite interposer further comprises a semiconductor layer (C2) disposed below the first interposer substrate and comprising a through via (see FIG. 3).
Regarding claim 5, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising, wherein the substrate is electrically coupled to the first interposer substrate (PDC) through the through via (BP1) and a bump structure (INC2).
Regarding claim 6, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), comprising, wherein the composite interposer further comprises a semiconductor layer (IC in FIG. 3) disposed over the second interposer substrate (PDN in FIG. 3) and comprising a through via, wherein the semiconductor layer is electrically coupled to the semiconductor die through the through via and a bump structure (see FIG. 3).
Regarding claim 7, Lee shows a semiconductor package structure (package structure 100 in FIG. 3), further comprising a conductive pad (P in FIG. 3) disposed below the first interposer substrate (PDC in FIG. 3) and electrically coupling the substrate (substrate 20) to the first interposer substrate (PDC).
Regarding claim 8, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising: a substrate (substrate 20); a composite interposer (PDC in FGI. 3) disposed over the substrate (substrate 20) and comprising: a first interposer substrate (C2) comprising a first conductive via (BP2), wherein the first conductive via has a first inclined sidewall (see FIG. 3); and a second interposer substrate (C1) bonded to the first interposer substrate and comprising a second conductive via (BP1 in FIG. 3), wherein the second conductive via has a second inclined sidewall connected to the first inclined sidewall (see FIG. 3); a bump structure (INC2 in FIG. 3) electrically coupling the composite interposer to the substrate; and a first semiconductor die disposed over the composite interposer and electrically coupled to the composite interposer (see FIG. 3).
Regarding claim 9, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein the first inclined sidewall extends in a first direction, and the second inclined sidewall extends in a second direction different from the first direction (see FIG. 3).
Regarding claim 10, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein the first conductive via has a third inclined sidewall, and the second conductive via has a fourth inclined sidewall connected to the third inclined sidewall (see FIG. 3).
Regarding claim 11, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein the composite interposer further comprises: a first semiconductor layer bonded to the first interposer substrate and comprising a first through via electrically coupled to the bump structure; and a second semiconductor layer bonded to the second interposer substrate and comprising a second through via electrically coupled to the first semiconductor die (see FIG. 3).
Regarding claim 12, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein comprising a plurality of conductive pads disposed on opposite sides of the composite interposer and electrically coupled to the first through via and the second through via (see FIG. 3).
Regarding claim 13, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein sidewalls of the first semiconductor layer, the first interposer substrate, the second interposer substrate, and the second semiconductor layer are coplanar (see FIG. 3).
Regarding claim 14, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising a second semiconductor die electrically coupled to a third through via of the second semiconductor layer (see FIG. 3).
Regarding claim 15, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), further comprising a molding material surrounding the first semiconductor die and the second semiconductor die, wherein a sidewall of the molding material is coplanar with a sidewall of the composite interposer (see FIG. 3).
Regarding claim 16, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising a substrate (substrate 20); a first semiconductor layer (C2) disposed over the substrate (substrate 20); a first interposer substrate (PDC) disposed over the first semiconductor layer and comprising a first conductive via (BP2), wherein the first conductive via has a first width decreasing in a direction toward the substrate (substrate 20); a second interposer substrate ( PDN) bonded to the first interposer substrate and comprising a second conductive via (BP1), wherein the second conductive via has a second width increasing in the direction toward the substrate (substrate 20); a second semiconductor layer disposed over the second interposer substrate; and a semiconductor die disposed over the second semiconductor layer and electrically coupled to the first conductive via and the second conductive via (see FIG. 3).
Regarding claim 17, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), comprising wherein the second interposer substrate is bonded to first interposer substrate through hybrid bonding (see FIG. 3).
Regarding claim 18, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), further comprising a plurality of through vias extending in the first semiconductor layer and the second semiconductor layer (see FIG. 3).
Regarding claim 19, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), further comprising a molding material surrounding the semiconductor die, wherein a sidewall of the molding material is coplanar with sidewalls of the first semiconductor layer, the first interposer substrate, the second interposer substrate, and the second semiconductor layer (see FIG. 3).
Regarding claim 20, Lee shows a semiconductor package structure ( package structure 100 in FIG. 3), further comprising an underfill material extending between the substrate and the first semiconductor layer and covering an edge of the first semiconductor layer (see FIG. 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893