DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 10-12 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 8,664,978).
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Regarding claim 1, Lu et al disclose [see Fig. 3 above] a method, comprising: coupling [via Logic L1 & L2] a first signal (DC voltage/current from Test DC) to an impedance (impedance M1 or R1); determining a first average current of the first signal (DC voltage/current) through the impedance (M1 or R1) over a first time, the first average current corresponding to a duty cycle of the first signal (DC voltage/signal) [see col. 4, lines 20-67 and col. 5, lines 41-58]; coupling [via Logic L1 & L2] a second signal (periodic signal) to the impedance (M1 or R1); determining a second average current of the second signal (periodic signal) through the impedance (M1 or R1) over a second time, the second average current corresponding to a first duty cycle of the second signal (periodic signal) [see col. 4, lines 20-67; col. 5, lines20-38 and col. 6, lines 19-27]; determining the first duty cycle from the first average current and the second average current [see col. 3, lines 15-67 and col. 4, lines 20-41]; and averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal [see col. 3, lines 15-67 and col. 4, lines 20-41]. However, the prior art does not explicitly disclose determining a third average current of the second signal through the impedance over a third time, the third average current corresponding to a second duty cycle of the second signal and determining the second duty cycle from the first average current and the third average current. Although the prior art does not specifically disclose the claimed third average current, this feature is seen to be an inherent teaching of that device since in col. 6, lines 49-59 disclosed “…average current Iavg can be measured over many clock cycles….”and it is apparent that some type of determining a third average current must be presented for the circuit to function as intended.
Regarding claim 2, Lu et al disclose wherein coupling the first signal (DC voltage/current from Test DC) to the impedance (M1 or R1) includes coupling a DC signal to the impedance (M1 or R1) [see col. 4, lines 20-67 and col. 5, lines 41-58].
Regarding claim 3, Lu et al disclose wherein coupling the second signal (periodic signal) to the impedance (M1 or R1) includes coupling a periodic signal (periodic signal) to the impedance (M1 or R1) [see col. 4, lines 20-67; col. 5, lines20-38 and col. 6, lines 19-27].
Regarding claim 4, Lu et al disclose wherein determining the second average current of the second signal (periodic signal) through the impedance (M1 or R1) includes determining the second average current of the second signal (periodic signal) through the impedance (M1 or R1) to a reference voltage VSS [via IOUT terminal] over the second time [see col. 5, line 39 – col 6, line 5 and col. 6, lines 38-48].
Regarding claim 7, Lu et al disclose the second signal (periodic signal) through the impedance (M1 or R1) includes determining the average current of the second signal (periodic signal) through the impedance (M1or R1) from a power source VDD [not shown but see col. 5, lines 21-22] over the time. However, the prior art does not explicitly disclose determining a third average current of the second signal through the impedance over a third time, the third average current corresponding to a second duty cycle of the second signal and determining the second duty cycle from the first average current and the third average current. Although the prior art does not specifically disclose the claimed third average current, this feature is seen to be an inherent teaching of that device since in col. 6, lines 49-59 disclosed “…average current Iavg can be measured over many clock cycles….”and it is apparent that some type of determining a third average current must be presented for the circuit to function as intended.
Regarding claim 12, Lu et al disclose [see Fig. 3 above] a method, comprising: coupling [via Logic L1 & L2] a DC signal (DC voltage/current from Test DC) to an impedance (impedance M1 or R1); determining a first current of the DC signal (DC voltage/current) through the impedance (M1 or R1) [see col. 4, lines 20-67 and col. 5, lines 41-58]; coupling [via Logic L1 & L2] a periodic signal (periodic signal) to the impedance (M1 or R1); determining a second current of the periodic signal (periodic signal) through the impedance (M1 or R1) to a reference voltage VSS [via IOUT terminal] over a first number of cycles of the periodic signal (periodic signal) [see col. 4, lines 20-67; col. 5, lines20-38 and col. 6, lines 19-27]; determining the first duty cycle from the first current and the second current [see col. 3, lines 15-67 and col. 4, lines 20-41]; and averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal [see col. 3, lines 15-67 and col. 4, lines 20-41]. However, the prior art does not explicitly disclose determining a third current of the periodic signal through the impedance from a power source VDD over a second number of clock cycles of the periodic signal. Although the prior art does not specifically disclose the claimed third current, this feature is seen to be an inherent teaching of that device since in col. 6, lines 49-59 disclosed “…average current Iavg can be measured over many clock cycles….”and it is apparent that some type of determining a third average current must be presented for the circuit to function as intended.
Regarding claim 17, Lu et al disclose [see Fig. 3 above] a system comprising a logic circuit (logic gates L1 & L2) having at least one input configured to receive a first signal (DC voltage/current from Test DC) and a second signal (periodic signal) and an output configured to provide a first output signal that corresponds to the first signal (DC voltage/current) and a second output signal that corresponds to the second signal (periodic signal); an impedance (impedance M1 or R1) connected to the output and configured to receive the first output signal and the second output signal; and a measurement circuit [not shown but connected to output terminal IOUT] connected to the impedance (M1 or R1) and configured to determine a first average current through the impedance (M1 or R1) based on the first output signal, a second average current through the impedance (M1 or R1) to a reference voltage based on the second signal. However, the prior art does not explicitly disclose determining a third average current of the second signal through the impedance over a third time, the third average current corresponding to a second duty cycle of the second signal and determining the second duty cycle from the first average current and the third average current. Although the prior art does not specifically disclose the claimed third average current, this feature is seen to be an inherent teaching of that device since in col. 6, lines 49-59 disclosed “…average current Iavg can be measured over many clock cycles….”and it is apparent that some type of determining a third average current must be presented for the circuit to function as intended.
Regarding claim 18, Lu et al disclose wherein the measurement circuit [not shown but connected to output terminal IOUT] is configured to determine a first duty cycle of the second signal (periodic signal) from the first average current and the second average current, a second duty cycle of the second signal (periodic signal) from the first average current, and a duty cycle of the second signal based on an average of the first duty cycle and the second duty cycle [see col. 3, lines 15-67 and col. 4, lines 20-41].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for details.
Allowable Subject Matter
Claims 5-6, 8-9, 13-16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding claims 5-6, 13-14 and 19, the primary reason for the allowance of the claims is due to wherein determining the first duty cycle from the first average current and the second average current includes dividing the second average current by the first average current.
Regarding claims 8-9, 15-16 and 20, the primary reason for the allowance of the claims is due to wherein determining the second duty cycle from the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result and subtracting the first result from one to obtain a second result.
Regarding claim 10, the primary reason for the allowance of the claim is due to wherein the first time is equal to each of the second time and the third time.
Regarding claim 11, the primary reason for the allowance of the claim is due to wherein the second time is equal to the third time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERMELE M HOLLINGTON/Primary Examiner, Art Unit 2858
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