DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/12/2023 and 05/12/2025 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE FORMATION PROCESS INCLUDING SELECTIVE WORK FUNCTION METAL LAYER DEPOSITION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US PGPub 2019/0304848; herein known as Cheng) in view of Lavric et al. (US PGPub 2023/0290778; herein known as Lavric).
Regarding claim 1, Cheng teaches (Figs. 1A-8A) A method, comprising: receiving a workpiece comprising: a first plurality of nanostructures (Fig. 2A, 108A-C, [0042]) over a first region (Fig. 2A, 152, [0042]) of a substrate (Fig. 2A, 102, [0042]), and a second plurality of nanostructures (Fig. 2A, 108A-C, [0042]) over a second region (Fig. 2A, 150, [0042]) of the substrate; depositing a gate dielectric layer (Fig. 2A, 110, [0042]) over surfaces of each of the first plurality of nanostructures (Fig. 2A, 108A-C) and each of the second plurality of nanostructures (108A-C); depositing a first work function metal layer (Fig. 2A, 112, [0046]) over the first plurality of nanostructures over the first region (152) and the second plurality of nanostructures over the second region (150); depositing a first hard mask layer (Fig. 2A, 202, [0053]) over the first work function metal layer (Fig. 2A, partially shown, [0053]); selectively removing the first hard mask layer and the first work function metal layer over the first region (Fig. 6A, [0053, 0065]); selectively removing the first hard mask layer over the second region (Fig. 7A, [0067]); and depositing a third work function metal layer (802, [0046]) over the first plurality of nanostructures over the first region (152) and the second plurality of nanostructures over the second region (150).
Cheng does generally teach the concept of a two-work function metal method for depositing work function metal layers on GAA FETS, using standard masking techniques. Cheng, however, does not teach using a second work function metal, specifically that after the selectively removing of the first hard mask layer over the second region, depositing a second work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer over the first region. In short, these method limitations result in a second work function metal layer over the first region, created using standard masking processes.
Lavric teaches in analogous art, a CMOS device with distinct PMOS and NMOS regions having work function materials, that it is known in the art that one could perform an extra gate metal flow (i.e. performing an additional masking step) to form a work function metal only in the PMOS or NMOS regions ([0029]) (i.e. creating an additional work function metal layer). Lavric teaches that this process step has the predictable result of further tuning the work function of the GAA FET device ([0027]; i.e. tuning the threshold voltage for device optimization).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a second metal work function layer in one of the nanostructures in Cheng, as suggested by Lavric, to further tune the overall work function of the device, as both Cheng and Lavric has shown that doing so involves known methods with predictable results, namely tuning the threshold voltage of the gate structure. (Lavric [0026]). As a result, Cheng’s device as modified by Lavric’s teaching necessarily would then include the established method to create that second work function metal layer and therefore teaches after the selectively removing of the first hard mask layer over the second region, depositing a second work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer over the first region. (See also MPEP 2143 I. D.)
Regarding claim 4, Cheng in view of Lavric teaches the method of claim 1, wherein the first hard mask layer comprises aluminum oxide, but does not explicitly teach wherein the second hard mask layer comprise aluminum oxide. As discussed above in the rejection of claim 1, Cheng in view of Lavric teaches wherein the standard hard masking step of Cheng can be repeated in order to create an additional work function metal layer. Additionally, Cheng in view of Lavric teaches use of an appropriate dielectric hard masking material, such as aluminum oxide, which is a known material in the art (Lavric, [0107, 0118]). Absent a teaching of criticality of the chosen material, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Cheng in view of Lavric to include wherein the second hard mask layer comprise aluminum oxide, as a known hard masking material.
Regarding claim 5, Cheng in view of Lavric teaches the method of claim 1, wherein the third work function metal layer comprises aluminum (Al) (Cheng, [0046]).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lavric as applied to claim 1 above, and further in view of Bao et al. (US PGPub 2023/0187495; herein known as Bao).
Regarding claim 2, Cheng in view of Lavric teaches the method of claim 1, wherein the first work function metal layer comprises titanium nitride (TiN) (Cheng, [0046]) but does not explicitly teach and the second work function metal layer comprises titanium nitride.
Bao teaches wherein the second work function metal layer (23, [0063]) comprises the same material ([0072]) as the first work function metal layer (22, [0063]).
Because Cheng in view of Lavric and Bao are directed toward GAA FET manufacturing, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng in view of Lavric and of Bao in order to allow for work function tuning of the device by adding additional work function metal layers (Bao, [0032]).
Regarding claim 3, Cheng in view of Lavric teaches the method of claim 1, but does not explicitly teach wherein a composition of the first work function metal layer and a composition of the second work function metal layer are the same.
Bao teaches wherein a composition of the first work function layer (22, [0063]) and a composition of the second work function layer (23, [0063]) are the same ([0072]).
Because Chen in view of Lavric and Bao are both directed toward GAA FET manufacturing, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng in view of Lavric and of Bao in order to allow for work function tuning of the device by adding additional work function metal layers (Bao, [0032]).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lavric as applied to claim 1 above, and further in view of Chen et al. (US PGPub 2022/0278218; herein known as Chen).
Regarding claim 7, Cheng in view of Lavric teaches the method of claim 1 but does not explicitly teach further comprising: depositing a glue layer over the third work function metal layer; and depositing a gate cap layer over the glue layer.
Chen teaches (Fig. 22) depositing a glue layer (not shown, fill layer, [0039]) over the third work function metal layer (not shown, [0046]), and depositing a gate cap layer (260, [0039]) over the glue layer ([0039]).
Because Cheng in view of Lavric and Chen are both directed toward GAA FET work function deposition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng in view of Lavric and of Chen in order to reduce gate resistance (Chen, [0039]).
Regarding claim 9, Cheng in view of Lavric and Chen teaches the method of claim 7, wherein the gate cap layer (Chen, Fig. 22, 260, [0039]) comprises tungsten (W) ([0039]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lavric and Chen as applied to claim 7 above, and further in view of Hsu et al. (US PGPub 2021/0134950; herein known as Hsu).
Regarding claim 8, Cheng in view of Lavric and Chen teaches the method of claim 7 but does not explicitly teach wherein the glue layer comprises titanium nitride.
Hsu teaches (Fig. 26) wherein the glue layer (116, [0031]) comprises titanium nitride ([0031]).
Because Cheng in view of Lavric and Chen and Hsu are all directed toward GAA FET work function metal deposition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng in view of Chen and of Hsu in order to provide electrical coupling between the glue layer and the gate electrode structures while maintaining a constant threshold voltage ([0031]).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lavric and further in view of Hsu.
Regarding claim 10, Cheng teaches a method, comprising: receiving a workpiece comprising: a first plurality of nanostructures (Fig. 2A, 108A-C, [0042]), and a second plurality of nanostructures (Fig. 2A, 108A-C, [0042]) ; depositing a gate dielectric layer (Fig. 2A, 110, [0042]) over surfaces of each of the first plurality of nanostructures (108A-C) and each of the second plurality of nanostructures (108A-C); depositing a first work function metal layer (Fig. 2A, 112, [0046]) over the first plurality of nanostructures and the second plurality of nanostructures and in contact with the gate dielectric layer; depositing a first hard mask layer (Fig. 2A, 202, [0053]) over the first work function metal layer such that the first hard mask layer is spaced apart from the gate dielectric layer by the first work function metal layer (Fig. 2A, [0053]) selectively removing the first hard mask layer and the first work function metal layer among the first plurality of nanostructures; selectively removing the first hard mask layer (Fig. 6A, [0053, 0065]) among the second plurality of nanostructures; and depositing a third work function metal layer (802, [0046]) to wrap around each of the first plurality of nanostructures and over the second work function metal layer over the second plurality of nanostructures.
Cheng does generally teach the concept of a two-work function metal method for depositing work function metal layers on GAA FETS, using standard masking techniques. Cheng, however, does not teach using a second work function metal, specifically that after the selectively removing of the first hard mask layer over the second region, depositing a second work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer over the first region. In short, these method limitations result in a second work function metal layer over the first region, created using standard masking processes.
Lavric teaches in analogous art, a CMOS device with distinct PMOS and NMOS regions having work function materials, that it is known in the art that one could perform an extra gate metal flow (i.e. performing an additional masking step) to form a work function metal only in the PMOS or NMOS regions ([0029]) (i.e. creating an additional work function metal layer). Lavric teaches that this process step has the predictable result of further tuning the work function of the GAA FET device ([0027]; i.e. tuning the threshold voltage for device optimization).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a second metal work function layer in one of the nanostructures in Cheng, as suggested by Lavric, to further tune the overall work function of the device, as both Cheng and Lavric has shown that doing so involves known methods with predictable results, namely tuning the threshold voltage of the gate structure. (Lavric [0026]). As a result, Cheng’s device as modified by Lavric’s teaching necessarily would then include the established method to create that second work function metal layer and therefore teaches after the selectively removing of the first hard mask layer over the second region, depositing a second work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer over the first region. (See also MPEP 2143 I. D.)
Cheng in view of Lavric does not explicitly teach a first base fin and a second base fin, spaced apart from the first base fin by an isolation feature. Cheng does teach a finFET device.
Hsu teaches (Fig. 26) a first base fin (204, [0037]) and a second base fin (104, [0035]), spaced apart from the first base fin by an isolation feature (106a, [0023]).
Because Cheng in view of Lavric and Hsu are directed toward methods of forming GAA FET devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao and of Hsu in order to provide connection between the substrate and channel of the FET device (Hsu, [0037]).
Regarding claim 11, Cheng in view of Lavric and Hsu teaches method of claim 10, wherein, after the depositing of the gate dielectric layer (Cheng, Fig. 1A, 110, [0042]), a portion of the gate dielectric layer extends continuously from over the first base fin (Hsu, Fig. 26, 204) to over the second base fin (Hsu, Fig. 26, 104). Cheng shows the gate dielectric layer continuous along the entire base substrate.
Regarding claim 12, Cheng in view of Lavric and Hsu teaches the method of claim 10, wherein, after the depositing of the first work function metal layer (Cheng, Fig. 1A, 112, [0042]), a portion of the first work function metal layer extends continuously from over the first base fin (Hsu, Fig. 26, 204) to over the second base fin (Hsu, Fig. 26, 104). Cheng shows the first work function metal layer continuous along the entire base substrate.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Hsu.
Regarding claim 16, Bao teaches (Fig. 22, Figs. 1-22 show full method of forming device) a semiconductor structure, comprising: a substrate (1, [0037]); an isolation feature (2, [0037]) over the substrate, a first plurality of nanostructures (2201-4, 2204-4, [0045]); a second plurality of nanostructures (4, [0045]); a gate dielectric layer (6, [0048]) wrapping around each of the first plurality of nanostructures (2201-4), each of the second plurality of nanostructures (2204-4) as well as disposed over top surfaces of the isolation feature ([0048]); a first work function layer (22, [0063]) wrapping around each of the second plurality of nanostructures (4) and a second work function layer (23, [0063]) wrapping around each of the second plurality of nanostructures (4, [0063]) and filling spaces among the second plurality of nanostructures (pinches off space, [0072]); a third work function layer (102, [0082]) wrapping around each of the first plurality of nanostructures (2201-4) and over the layer that wraps around the second plurality of nanostructures (2204-4); ; and a gate cap layer (103, [0082]) over the glue layer, wherein an interface (33, [0053]) exists between the first work function layer and the second work function layer ([0032]).
Bao does not explicitly teach a first or second base fin disposed under the first or second nanostructures, respectively, or a glue layer disposed on the third work function layer.
Hsu teaches (Fig. 26) a first (204, [0037]) and second base fin (104, [0035]) disposed under the first (218a-d, [0092]) and second nanostructures (118a-d, [0092]) respectively.
Because Bao and Hsu are both directed toward NSFETs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao and of Hsu in order to provide connection between the substrate and channel of the FET device (Hsu, [0037]).
Hsu further teaches a glue layer (116, [0047]) disposed on the third work function layer (224, [0047]).
Because Bao and Hsu are both directed toward NSFETs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Bao and of Hsu in order to provide a conductive material around the gate structures that does not impact the work function of the underlying metal structures (Hsu, [0091]).
Regarding claim 17, Bao in view of Hsu teaches (Fig. 22) the semiconductor structure of claim 16, wherein the first work function layer (22, [0063]) and the second work function layer (23, [0063]) comprise a p-type work function material ([0049]).
Regarding claim 18, Bao in view of Hsu teaches (Fig. 22) the semiconductor structure of claim 17, wherein the third work function layer (102, [0083]) comprises an n-type work function material ([0083]).
Regarding claim 19, Bao in view of Hsu teaches the semiconductor structure of claim 17, wherein a composition of the first work function layer (22, [0063]) and a composition of the second work function layer (23, [0063]) are the same ([0072]).
Regarding claim 20, Bao in view of Hsu teaches the semiconductor structure of claim 16, wherein the interface (33, [0053]) comprises an oxide form of a metal composition in the first work function layer ([0053]).
Allowable Subject Matter
Claims 6 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the cited prior art of record does not teach or fairly suggest, along with the other claimed features a method further comprising before the selectively removing of the first hard mask layer and the first work function metal layer over the first region, trimming the first hard mask layer; and before the selectively removing of the second hard mask layer and the second work function metal layer over the first region, trimming the second hard mask layer.
Both Chen and Lavric teach a single selective etch step for removal of the hard mask layer, in order to reduce the number of process steps and to avoid unwanted etching of the gate structures. Chu et al. (US PGPub 2022/0320089; herein known as Chu) teaches a trimming step, but teaches wherein the trimming step removes the entire hard mask layer and selectively removes a portion of a sacrificial layer. It would not be obvious to one of ordinary skill in the art to equate the partial removal of a sacrificial layer to the partial removal of a hard mask layer, as the etch processes are not equivalent, and may impact the resulting devices differently. Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Regarding claim 13, the cited prior art of record does not teach or fairly suggest, along with the other claimed features a method further comprising: trimming the first hard mask layer to expose portions of the first work function metal layer over a topmost surface and sidewalls of the first plurality of nanostructures.
Both Chen and Lavric teach a single selective etch step for removal of the hard mask layer, in order to reduce the number of process steps and to avoid unwanted etching of the gate structures. Chu teaches a trimming step, but teaches wherein the trimming step removes the entire hard mask layer and selectively removes a portion of a sacrificial layer, only exposing the top of the first work function metal over a topmost surface of a topmost nanostructure, not including the sidewalls of topmost of the other of the plurality of nanostructures. Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claim 14 is allowable as dependent on claim 13.
Regarding claim 15, the cited prior art of record does not teach or fairly suggest, along with the other claimed features trimming the second hard mask layer to expose portions of the second work function metal layer over a topmost surface and sidewalls of the first plurality of nanostructures.
Both Chen and Lavric teach a single selective etch step for removal of the hard mask layer, in order to reduce the number of process steps and to avoid unwanted etching of the gate structures. Chu teaches a trimming step, but teaches wherein the trimming step removes the entire hard mask layer and selectively removes a portion of a sacrificial layer, only exposing the top of of the first work function metal over a topmost surface of a topmost nanostructure, not including the sidewalls of topmost of the other of the plurality of nanostructures. Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed
Conclusion
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812