Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on January 23, 2026 is acknowledged. Claims 8-10 are withdrawn from further consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Boettcher et al. (Implementation of chip embedding processes for the creation of miniaturized system-in-packages) in view of Liu (US 2021/0134748).
Regarding Claim 1:
Boettcher discloses a chip package structure, comprising:
a first chip (chip bonded to copper substrate, See figs. 1a-1e and Embedded Chip Modules section),
a first insulating layer (epoxy layer, See figs. 1b-1e and Lamination Process and Embedding Materials section), covering the first chip and having a first upper surface (upper surface of the epoxy layer, See figs. 1b-1e) and a first lower surface (lower surface of the epoxy layer, See figs. 1b-1e) opposite to each other;
a first patterned conductive layer (overlaying copper layer, See fig. 1c and Lamination Process and Embedding Materials section. The examiner notes that the overlaying copper layer is shown patterned in fig. 1c), disposed on the first upper surface of the first insulating layer;
a second patterned conductive layer (copper substrate, See fig. 1e and Embedded Chip Modules section. The examiner notes that the copper substrate is shown patterned in fig. 1e.), disposed on the first lower surface of the first insulating layer;
a plurality of first conductive via structures (through vias located to the right and left of the chip, See figs. 1d-1e), passing through the first insulating layer and electrically connected to the first patterned conductive layer and the second patterned conductive layer (See figs. 1d-1e); and
a plurality of second conductive via structures (micro vias located on the chip, See figs. 1d-1e and Via Opening and Filling section), disposed inside the first insulating layer and electrically connected to the first chip and the first patterned conductive layer (See figs. 1d-1e).
Boettcher does not disclose the first chip, having a plurality of first through silicon vias;
a second chip, directly disposed on the first chip, wherein the first chip is electrically connected to the second chip through the plurality of first through silicon vias;
a plurality of first hybrid bonding pads, formed between the first chip and the second chip, wherein the first chip is bonded onto the second chip through the plurality of first hybrid bonding pads;
Liu discloses the first chip (3rd Semiconductor Structure, See fig. 2A and paragraphs 46), having a plurality of first through silicon vias (third via structure and via structure located to the left of the third via structure, See fig. 2A, ref. no. 250 and paragraphs 46-47);
a second chip (2nd Semiconductor Structure, See fig. 2A and paragraph 45), directly disposed on the first chip, wherein the first chip is electrically connected to the second chip through the plurality of first through silicon vias (electrical signal can be transmitted from/to the semiconductor structure through the via structure, See paragraph 47) ;
a plurality of first hybrid bonding pads (a plurality of bonding contacts on 3rd Semiconductor Structure together with a plurality of bonding contacts on 2nd Semiconductor Structure, See fig. 2A, ref. nos. 234 and 236), formed between the first chip and the second chip, wherein the first chip is bonded onto the second chip through the plurality of first hybrid bonding pads ( bonding between the 3rd Semiconductor Structure and the 2nd Semiconductor Structure is hybrid bond, See paragraphs 42 and 46).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package structure of Boettcher to include the first chip, having a plurality of first through silicon vias; a second chip, directly disposed on the first chip, wherein the first chip is electrically connected to the second chip through the plurality of first through silicon vias; a plurality of first hybrid bonding pads, formed between the first chip and the second chip, wherein the first chip is bonded onto the second chip through the plurality of first hybrid bonding pads as taught by Liu in order to package more chips together without increasing the layout area occupied by the chips through vertically stacking chips.
Regarding Claim 2:
Liu discloses wherein the first chip has a first surface (bottom surface of the 3rd Semiconductor Structure, See fig. 2A), the second chip has a second surface (top surface of the 2nd Semiconductor Structure, See fig. 2A), and the first surface directly contacts the second surface (the 3rd Semiconductor Structure is bonded to the 2nd Semiconductor Structure in a face-down manner at a bonding interface, See fig. 2A, ref. no. 206 and paragraph 37).
Regarding Claim 7:
Boettcher discloses a die attach film (bonding layer between the chip and the copper substrate, See figs. 1a-1e and Chip Placement and Bonding section), disposed between the second chip and the second patterned conductive layer, wherein the second chip is fixed onto the second patterned conductive layer through the die attach film.
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Boettcher et al. (Implementation of chip embedding processes for the creation of miniaturized system-in-packages) in view of Liu (US 2021/0134748) further in view of Munding et al. (WO 2023/179088 A1).
Regarding Claim 3:
The above stated combination of Boettcher and Liu discloses the above stated chip package structure.
The above stated combination of Boettcher and Liu does not disclose a build-up structure; and a core substrate, comprising a core layer and a plurality of third conductive via structures, wherein the core layer is disposed between the build-up structure and the second patterned conductive layer, and the plurality of third conductive via structures pass through the core layer and are electrically connected to the build-up structure and the second patterned conductive layer.
Munding discloses a build-up structure (first joining member, See fig. 7, ref. no. 120, page 46 lines 29-30, page 53 lines 33-35, and page 54 lines 1-13); and a core substrate (hybrid bond sheet, See fig. 7, ref. no. 210, page 53 lines 33-35, and page 54 lines 1-13), comprising a core layer (core layer, See fig. 7, ref. no. 210 and page 46 lines 32-32) and a plurality of third conductive via structures (plurality of customized vertical through-connections, See fig. 7, ref. no. 212), wherein the core layer is disposed between the build-up structure and the second patterned conductive layer (the core layer of the hybrid bond sheet is located between the first joining member and the second joining member, See fig. 7, ref. nos. 110, 120, 210), and the plurality of third conductive via structures pass through the core layer and are electrically connected to the build-up structure and the second patterned conductive layer (the vertical through-connections are form an electrically conductive connection between the first joining member and the second joining member, See page 47 lines 21-24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package structure of Boettcher and Liu to include a build-up structure; and a core substrate, comprising a core layer and a plurality of third conductive via structures, wherein the core layer is disposed between the build-up structure and the second patterned conductive layer, and the plurality of third conductive via structures pass through the core layer and are electrically connected to the build-up structure and the second patterned conductive layer as taught by Munding in order to increase power density and efficiency in the chip package structure. (See Munding page 1 lines 14-16.)
Regarding Claim 6:
The examiner now points out that the thickness of the core substrate is a result effective variable because adjusting the thickness of the core substrate adjusts the spread of heat. The examiner next points out that thickness of the core substrate is recognized by the prior art as a result-effective variable (adjusting the thickness of the hybrid bond sheet adjust the spread of heat, See Munding page 53 lines 4-8). The examiner notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a thickness of the core substrate greater than a thickness of the build-up structure for better spreading of heat.
Allowable Subject Matter
Claim 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the disclosures and illustrations of Boettcher, Liu, and/or Munding as discussed above fail to or suggest the build-up structure having a third chip, having a plurality of second through silicon vias; a fourth chip, directly disposed on the third chip, wherein the third chip is electrically connected to the fourth chip through the plurality of second through silicon vias; a plurality of second hybrid bonding pads, formed between the third chip and the fourth chip, wherein the third chip is bonded onto the fourth chip through the plurality of second hybrid bonding pads; a second insulating layer, covering the third chip and the fourth chip and having a second upper surface and a second lower surface opposite to each other; a third patterned conductive layer, disposed on the second upper surface of the second insulating layer; a fourth patterned conductive layer, disposed on the second lower surface of the second insulating layer and directly contacting the core layer, wherein the plurality of third conductive via structures are electrically connected to the second patterned conductive layer and the fourth patterned conductive layer; a plurality of fourth conductive via structures, passing through the second insulating layer and electrically connected to the third patterned conductive layer and the fourth patterned conductive layer; and a plurality of fifth conductive via structures, disposed inside the second insulating layer and electrically connected to the third chip and the third patterned conductive layer. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Boettcher, Liu, and/or Munding to teach and/or suggest the limitations of claim 4. Therefore, claim 4 includes allowable subject matter.
With respect to claim 5, the disclosures and illustrations of Boettcher, Liu, and/or Munding as discussed above fail to teach or suggest the build-up structure having a second insulating layer, having a second upper surface and a second lower surface opposite to each other; a first patterned circuit layer, disposed on the second upper surface of the second insulating layer and directly contacting the core layer, wherein the plurality of third conductive via structures are electrically connected to the second patterned conductive layer and the first patterned circuit layer; a second patterned circuit layer, disposed inside the second insulating layer; a third patterned circuit layer, disposed on the second lower surface of the second insulating layer; a plurality of fourth conductive via structures, disposed inside the second insulating layer and electrically connected to the first patterned circuit layer and the second patterned circuit layer; a plurality of fifth conductive via structures, disposed inside the second insulating layer and electrically connected to the second patterned circuit layer and the third patterned circuit layer; and a plurality of sixth conductive via structures, disposed inside the second insulating layer and electrically connected to the first patterned circuit layer and the third patterned circuit layer. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Boettcher, Liu, and/or Munding to teach and/or suggest the limitations of claim 5. Therefore, claim 5 includes allowable subject matter.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899