DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al (U.S. Patent #9761507).
With respect to claim 1, Huang teaches an apparatus, comprising:
a first lead (Fig. 1A, 108 and Col 4 Ln 17-26) having a first chip attachment portion and a second chip attachment portion (Fig. 1A, i.e. bottom surface and top surface of 108, respectively);
a second lead (Fig. 1A, 110) having a third chip attachment portion (i.e. bottom surface of 110);
a third lead (Fig. 1A, 106) having a fourth chip attachment portion (i.e. top surface of 106); and
wherein a first semiconductor chip (Fig. 1A, 102) is configured to be conductively coupled (Fig. 1A, 123 and 122; Col 4 Ln 43-56) to the first chip attachment portion and the third chip attachment portion, and a second semiconductor chip (Fig. 1A, 104) is configured to be conductively coupled (Fig. 1A, 124 and 125) to the second chip attachment portion and the fourth chip attachment portion.
With respect to claim 2, Huang teaches a first substrate layer (Fig. 1A, left side portion of 108) positioned over the third chip attachment portion and the first semiconductor chip.
With respect to claim 3, Huang teaches a second substrate layer (Fig. 1A, top 134) sandwiched between the first chip attachment portion and the second chip attachment portion.
With respect to claim 4, Huang teaches a third substrate layer (Fig. 1A, 142) positioned over the fourth chip attachment portion and the second semiconductor chip.
With respect to claim 5, Huang teaches that the second lead (Fig. 1A, 106) is conductively separate from the third lead (Fig. 1A, 110).
With respect to claim 6, Huang teaches a first conductive channel (Fig. 1A, electrical path A11 through A21) conductively coupling the first lead, the first chip attachment portion, the first semiconductor chip, the third chip attachment portion, and the second lead.
With respect to claim 7, Huang teaches a second conductive channel (Fig. 1A, electrical path A11 through A22) conductively coupling the first lead, the second chip attachment portion, the second semiconductor chip, the fourth chip attachment portion, and the third lead.
With respect to claim 8, Huang teaches that at least one of the first lead, the first chip attachment portion, the second chip attachment portion, the second lead, the third chip attachment portion, the third lead, and the fourth chip attachment portion (Fig. 1A, surfaces of 106, 108, and 110) include at least one of the following: zinc, copper, silver, aluminum, metals, alloys thereof, and/or any combinations thereof (Col 4 Ln 18-24).
With respect to claim 9, Huang teaches that at least one of the first and second semiconductor chips include one or more respective working areas (Fig. 1A, inner/central portions 102-1/2 and 104-1/2 of chips 102/104), wherein at least one of the first, second, third, and fourth chip attachment portions are configured to be conductively coupled to the one or more respective working areas of corresponding first and second semiconductor chips.
With respect to claim 10, Huang teaches that at least one of the first, second and third leads are configured to be coupled to at least one of the following: a substrate, a printed circuit board (Fig. 1A, the bottom coplanar anode/cathode 150/160 and solder mask 144 allow the package 100 to be mounted by solder on a flat PCB for electrical connections), and any combination thereof.
With respect to claim 11, Huang teaches a first fill layer (Fig. 1A, bottom portion of 126 and Col 5 Ln 14-18) is configured to be formed for encapsulating the first semiconductor chip (Fig. 1A, 102), the first chip attachment portion and the third chip attachment portion.
With respect to claim 12, Huang teaches a second fill layer (Fig. 1A, top portion of 126) is configured to be formed for encapsulating the second semiconductor chip (Fig. 1A, 104), the second chip attachment portion and the fourth chip attachment portion.
With respect to claim 13, Huang teaches that at least one of the first and second fill layers are manufactured from at least one of the following: an epoxy compound, a plastic, and any combination thereof (Col 5 Ln 14-18).
With respect to claim 14, Huang teaches that the apparatus is configured to be a surface mounted apparatus (Fig. 1A, the coplanar anode/cathode 150/160 and solder mask 144 allow the package 100 to be mounted by solder on a flat surface).
With respect to claim 17, Huang teaches a method, comprising:
providing one or more substrate layers (Fig. 1A, 150 and/or 160; i.e. bottommost supporting portions), the one or more substrate layers being coupled to one or more chip connection portions (i.e. bottom surface and top surface of 108, 106, and/or 110);
providing one or more semiconductor chips (Fig. 1A, 102 and/or 104; and Col 3 Ln 45-52);
coupling at least one of the one or more semiconductor chips to at least one of the one or more chip connection portions (Fig. 1, 122-125; Col 4 Ln 43-56);
forming one or more fill layers (Fig. 1A, 126 and Col 5 Ln 14-18) to encapsulate the coupled at least one of the one or more semiconductor chips and at least one of the one or more chip connection portions;
applying one or more coating layers (Fig. 1A, 142 and/or 144) to at least one of the one or more formed fill layers; and
forming one or more leads (Fig. 1A, 106, 108, and 110; and Col 4 Ln 17-26) in the encapsulated at least one of the one or more semiconductor chips and at least one of the one or more chip connection portions, the one or more leads being connected to at least one of the one or more chip connection portions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang, in view of Tijssen et al (U.S. Pub #2013/0334695).
With respect to claim 15, Huang does not teach that at least one of the first and second semiconductor chips include at least one transient voltage suppression device.
Tijssen teaches that a chip comprising a rectifying device can be configured as a transient voltage device (Paragraph 19 and 24). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure a rectifying chip of Huang as a transient voltage device as taught by Tijssen in order to protect against transient voltages (Paragraph 3).
With respect to claim 16, Huang teaches an multiple channel device (Fig. 1A, A21 and A22), comprising:
a first lead (Fig. 1A, 108 and Col 4 Ln 17-26) having a first chip attachment portion and a second chip attachment portion (Fig. 1A, i.e. bottom surface and top surface of 108, respectively);
a second lead (Fig. 1A, 110) having a third chip attachment portion (i.e. bottom surface of 110);
a third lead (Fig. 1A, 106) having a fourth chip attachment portion (i.e. top surface of 106); and
wherein a first semiconductor chip (Fig. 1A, 102 and Col 3 Ln 45-52) is configured to be conductively coupled (Fig. 1A, 123 and 122; Col 4 Ln 43-56) to the first chip attachment portion and the third chip attachment portion, and a second semiconductor chip (Fig. 1A, 104) is configured to be conductively coupled (Fig. 1A, 124 and 125) to the second chip attachment portion and the fourth chip attachment portion.
Huang does not teach a multiple channel protection device.
Tijssen teaches that a chip comprising a rectifying device can be configured as a protection device (Paragraph 19 and 24). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure a rectifying chip of Huang as a protection device as taught by Tijssen in order to protect against transient voltages (Paragraph 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812