DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 06/24/26. Claims 1-5, 7, 8, and 16-28 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, 16, 21, 24-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (US PGPub 2022/0285414, hereinafter referred to as “Shin”).
Shin discloses the semiconductor device as claimed. See figures 1-9B and corresponding text, where Shin teaches, in claim 1, a semiconductor structure, comprising:
a photodiode (PD) in a substrate (300); (figure 5A; [0049], [0053])
a floating node (FD) including an n-type doping region (figure 5B; [0059]);
an isolation structure (306) surrounding the photodiode (PD) (figure 5B; [0056]); and
a p-type doping region (308), between the n-type doping region and the isolation structure (304), and configured to absorb excess charge from the isolation structure (306), (figure 5B; [0052-0056])
wherein the isolation structure (306) extends into the substrate (300) to a first depth (figure 5B; [0052-0056]), and the p-type doping region (308) extends into the substrate (300) to a second depth less than the first depth (figure 5B; [0052-0056]).
Shin teaches, in claim 2, further comprising:
a transfer gate (330) connected to the floating node (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 3, wherein the floating node further includes a drain extension region (figures 5A-5D; [0060], the photoelectric conversion element PD acts as a drain).
Shin teaches, in claim 4, further comprising:
at least one film (302/304) adjacent to the p-type doping region and over a dielectric material of the isolation structure (306) (figure 5C; [0052], may include multiple layers).
Shin teaches, in claim 5, wherein the at least one film includes a first film and a second film, and the p-type doping region contacts the first film and the second film (figure 5C; [0052], may include multiple layers).
Shin teaches, in claim 7, further comprising:
a conductive structure (332) that contacts a portion of the substrate adjacent to the isolation structure (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 8, further comprising:
a conductive structure (350) that contacts a portion of a film over a dielectric material of the isolation structure (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 16, a semiconductor structure, comprising:
a photodiode (PD) in a substrate (300);
a transfer gate (330) associated with a drain region;
an isolation structure (306) surrounding the photodiode (PD); and
a p-type doping region (308), between the drain region and the isolation structure (306), and configured to absorb excess charge from the isolation structure, wherein the isolation structure is a deep trench isolation structure (304) extending through a full height of the substrate from a front side of the substrate to a back side of the substrate (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 21, a semiconductor structure, comprising:
a photodiode (PD) in a substrate (300);
a p-type doping region (308) adjacent to an isolation structure (306) in a substrate (300);
a floating node (FD) including an n-type doping region;
an isolation structure (306) surrounding the photodiode;
a p-type doping region (308) between the n-type doping region and the isolation structure; and
at least one conductive structure (334) associated with the floating node;
wherein the isolation structure (306) has a first width, and the p-type doping region has a second width less than the first width (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 24, further comprising:
a gate material (350) over the substrate, wherein at least one film separates the gate material from at least one dielectric material of the isolation structure (figure 5D; [0065]).
Shin teaches, in claim 25, wherein the photodiode (PD)is on a backside back side of the substrate (300), and wherein the isolation structure (306) is associated with a frontside front side of the substrate (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 26, wherein the at least one conductive structure (332) comprises a via or a contact plug electrically connected to the n-type doping region (figures 5A-5D; [0049-0061]).
Shin teaches, in claim 27, wherein the floating node further includes a drain extension region adjacent to the n-type doping region (figures 5A-5D; [0049-0061]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17-20 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US PGPub 2022/0285414, hereinafter referred to as “Shin”) as applied to claim 16 above.
Shin discloses the semiconductor device substantially as claimed. See the rejection above.
However, Shin fails to explicitly show, in claim 17, wherein a ratio of a depth of the p-type doping region to a width of the p-type doping region is in a range from approximately 0.6 to approximately 200.0.
Shin teaches, in claim 17, forming a p-type doping region (cell p-well region 380) using conventional deposition techniques (figures 5A-5D; [0049-0061]). In addition, Shin provides the advantage of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a depth of the p-type doping region to a width of the p-type doping region is in a range from approximately 0.6 to approximately 200.0, in the device of Shin, according to the teachings of Shin, with the motivation of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Shin fails to explicitly show, in claim 18, wherein a concentration associated with the p-type doping region is in a range from approximately 1.0 x 1017 inverse cubic centimeters (cm-3) to approximately 1.0 x 1021 cm-3.
Shin teaches, in claim 18, forming a p-type doping region (cell p-well region 380) using conventional deposition techniques (figures 5A-5D; [0049-0061]). In addition, Shin provides the advantage of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a concentration associated with the p-type doping region is in a range from approximately 1.0 x 1017 inverse cubic centimeters (cm-3) to approximately 1.0 x 1021 cm-3, in the device of Shin, according to the teachings of Shin, with the motivation of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Shin fails to show, in claim 19, wherein a ratio of a depth of the isolation structure to a depth of the p-type doping region is in a range from approximately 2.50 to approximately 266.67.
Shin teaches, in claim 19, forming a p-type doping region (cell p-well region 380) using conventional deposition techniques (figures 5A-5D; [0049-0061]). In addition, Shin provides the advantage of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a depth of the isolation structure to a depth of the p-type doping region is in a range from approximately 2.50 to approximately 266.67, in the device of Shin, according to the teachings of Chen, with the motivation of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Shin fails to show, in claim 20, wherein a ratio of the isolation structure to a width of the p-type doping region is in a range from approximately 1.0 to approximately 60.0.
Shin teaches, in claim 20, forming a p-type doping region (cell p-well region 380) using conventional deposition techniques (figures 5A-5D; [0049-0061]). In addition, Shin provides the advantage of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a width of the isolation structure to a width of the p-type doping region is in a range from approximately 1.0 to approximately 60.0, in the device of Shin, according to the teachings of Chen, with the motivation of with the motivation of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Shin fails to teach, in claim 28, wherein a ratio of the first depth to the second depth is in a range from approximately 2.50 to approximately 266.67.
Shin teaches, in claim 28, forming a p-type doping region (cell p-well region 380) using conventional deposition techniques (figures 5A-5D; [0049-0061]). In addition, Shin provides the advantage of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of the first depth to the second depth is in a range from approximately 2.50 to approximately 266.67, in the device of Shin, according to the teachings of Shin, with the motivation of improving a charge transfer efficiency between a photoelectric conversion element and a floating diffusion. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Claim(s) 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US PGPub 2022/0285414, hereinafter referred to as “Shin”) as applied to claim 21 above, and further in view of Fan (US PGPub 2023/087464, hereinafter referred to as “Fan”).
Shin discloses the semiconductor device substantially as claimed. See the rejection above.
In addition, Shin shows, in claim 22, further comprising:
a first chip including the photodiode, the floating node, and the at least one conductive structure (figures 5A-5D; [0049-0061]).
However, Shin fails to show, in claim 22, a second chip, including an integrated circuit, bonded to the first chip.
Fan teaches, in claim 22, stacking a logic die, a memory die and a sensor die to form an optical semiconductor device (figure 16; [0101]). In addition, Fan provides the advantages of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies and reducing energy consumption from signal transferring ([0007]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate a second chip, including an integrated circuit, bonded to the first chip, in the device of Shin, according to the teachings of Fan, with the motivation of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies that reduce energy consumption from signal transferring.
Shin fails to show, in claim 23, further comprising:
a first chip including the photodiode and the floating node a second chip including an integrated circuit; and
a third chip, including at least one transistor, bonded to the first chip and the second chip.
Fan teaches, in claim 22, stacking a logic die, a memory die and a sensor die to form an optical semiconductor device (figure 16; [0101]). In addition, Fan provides the advantages of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies and reducing energy consumption from signal transferring ([0007]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate further comprising:
a first chip including the photodiode and the floating node a second chip including an integrated circuit; and
a third chip, including at least one transistor, bonded to the first chip and the second chip, in the device of Shin, according to the teachings of Fan, with the motivation of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies that reduce energy consumption from signal transferring.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 5, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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