DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claim 1-5, 7, 8, and 16-27 in the reply filed on 2/03/26 is acknowledged. Applicant has cancelled non-elected Invention.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 10/13/23, 03/05/25, and 9/08/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, 16, 21 and 24-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2022/031068, hereinafter referred to as “Chen”).
Chen disclose the semiconductor device as claimed. See figures 1-7 and corresponding text, where Chen teaches, in claim 1, a semiconductor structure, comprising:
a photodiode (304) in a substrate (302); (figure 3A; [0043])
a floating node (310/312) including an n-type doping region (figure 3A; [0039]);
an isolation structure (324) surrounding the photodiode (304); (figure 3A; [0044]) and
a p-type doping region (320), between the n-type doping region (310/312) of the floating node and the isolation structure (324), and configured to absorb excess charge from the isolation structure (figure 3A; [0043]).
Chen teaches, in claim 2, further comprising:
a transfer gate (314) connected to the floating node (figure 3A; [0040-0043]).
Chen teaches, in claim 3, wherein the floating node further includes a drain extension region (310) (figure 3A; [0039]).
Chen teaches, in claim 4, further comprising:
at least one film adjacent to the p-type doping region and over a dielectric material of the isolation structure (figure 3A; [0048]).
Chen teaches, in claim 5, wherein the at least one film includes a first film and a second film, and the p-type doping region contacts the first film and the second film (figure 3A; [0048]).
Chen teaches, in claim 7, further comprising:
a conductive structure (338) that contacts a portion of the substrate adjacent to the isolation structure (figure 3A; [0049]).
Chen teaches, in claim 8, further comprising:
a conductive structure that contacts a portion of a film over a dielectric material of the isolation structure (figure 3A; [0049]).
Chen teaches, in claim 16, a semiconductor structure, comprising:
a photodiode (304) in a substrate (302); (figure 3A; [0043])
a transfer gate (318) associated with a drain region (310/312); (figure 3A; [0042-0043])
an isolation structure (324) surrounding the photodiode (304); (figure 3A; [0044]); and
a p-type doping region (320), between the drain region (310/312) and the isolation structure (324), and configured to absorb excess charge from the isolation structure (figure 3A; [0043]).
Chen teaches, in claim 21, a semiconductor structure, comprising: (figure 3A; [0039-0044])
a p-type doping region (320) adjacent to an isolation structure (324) in a substrate (302);
a floating node (310/312) including an n-type doping region;
a photodiode (304) in the substrate (3023); and
at least one conductive structure (314) associated with the floating node (310/312).
Chen teaches, in claim 24, further comprising:
a gate material over the substrate, wherein at least one film separates the gate material from at least one dielectric material of the isolation structure (figure 3A; [0043]).
Chen teaches, in claim 25, wherein the photodiode is on a backside of the substrate, and wherein the isolation structure is associated with a frontside of the substrate (figure 3A; [0043]).
Chen teaches, in claim 26, wherein the at least one conductive structure comprises a via or a contact plug electrically connected to the n-type doping region (figure 3A; [0043]).
Chen teaches, in claim 27, wherein the floating node further includes a drain extension region adjacent to the n-type doping region (figure 3A; [0043]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2022/031068, hereinafter referred to as “Chen”) as applied to claim 16 above, and further in view of Chen et al. (US PGPub 2022/031068, hereinafter referred to as “Chen”).
Chen discloses the semiconductor device substantially as claimed. See the rejection above.
However, Chen fails to explicitly show, in claim 17, wherein a ratio of a depth of the p-type doping region to a width of the p-type doping region is in a range from approximately 0.6 to approximately 200.0.
Chen teaches, in claim 17, forming a p-type doping region (cell p-well region 320) using conventional deposition techniques (figures 1 and 4B; [0062]). In addition, Chen provides the advantage of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a depth of the p-type doping region to a width of the p-type doping region is in a range from approximately 0.6 to approximately 200.0, in the device of Chen, according to the teachings of Chen, with the motivation of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Chen fails to explicitly show, in claim 18, wherein a concentration associated with the p-type doping region is in a range from approximately 1.0 x 1017 inverse cubic centimeters (cm-3) to approximately 1.0 x 1021 cm-3.
Chen teaches, in claim 18, forming a p-type doping region (cell p-well region 320) using conventional deposition techniques (figures 1 and 4B; [0062]). In addition, Chen provides the advantage of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a concentration associated with the p-type doping region is in a range from approximately 1.0 x 1017 inverse cubic centimeters (cm-3) to approximately 1.0 x 1021 cm-3, in the device of Chen, according to the teachings of Chen, with the motivation of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Chen fails to show, in claim 19, wherein a ratio of a depth of the isolation structure to a depth of the p-type doping region is in a range from approximately 2.50 to approximately 266.67.
Chen teaches, in claim 19, forming a p-type doping region (cell p-well region 320) using conventional deposition techniques (figures 1 and 4B; [0062]). In addition, Chen provides the advantage of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a depth of the isolation structure to a depth of the p-type doping region is in a range from approximately 2.50 to approximately 266.67, in the device of Chen, according to the teachings of Chen, with the motivation of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Chen fails to show, in claim 20, wherein a ratio of a width of the isolation structure to a width of the p-type doping region is in a range from approximately 1.0 to approximately 60.0.
Chen teaches, in claim 20, forming a p-type doping region (cell p-well region 320) using conventional deposition techniques (figures 1 and 4B; [0062]). In addition, Chen provides the advantage of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate wherein a ratio of a width of the isolation structure to a width of the p-type doping region is in a range from approximately 1.0 to approximately 60.0, in the device of Chen, according to the teachings of Chen, with the motivation of providing electrical isolation and/or optical isolation between the pixel sensor and adjacent sensors. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Claim(s) 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2022/031068, hereinafter referred to as “Chen”) as applied to claim 21 above, and further in view of Fan (US PGPub 2023/087464, hereinafter referred to as “Fan”).
Chen discloses the semiconductor device substantially as claimed. See the rejection above.
In addition, Chen shows, in claim 22, further comprising:
a first chip including the photodiode, the floating node, and the at least one conductive structure (figure 3A; [0043]);
However, Chen fails to show, in claim 22, a second chip, including an integrated circuit, bonded to the first chip.
Fan teaches, in claim 22, stacking a logic die, a memory die and a sensor die to form an optical semiconductor device (figure 16; [0101]). In addition, Fan provides the advantages of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies and reducing energy consumption from signal transferring ([0007]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate a second chip, including an integrated circuit, bonded to the first chip, in the device of Chen, according to the teachings of Fan, with the motivation of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies that reduce energy consumption from signal transferring.
Chen fails to show, in claim 23, further comprising:
a first chip including the photodiode and the floating node a second chip including an integrated circuit; and
a third chip, including at least one transistor, bonded to the first chip and the second chip.
Fan teaches, in claim 22, stacking a logic die, a memory die and a sensor die to form an optical semiconductor device (figure 16; [0101]). In addition, Fan provides the advantages of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies and reducing energy consumption from signal transferring ([0007]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to incorporate further comprising:
a first chip including the photodiode and the floating node a second chip including an integrated circuit; and
a third chip, including at least one transistor, bonded to the first chip and the second chip, in the device of Chen, according to the teachings of Fan, with the motivation of reserving the sensor die for optical sensing functions to simplify the complexities of fabrication of the sensor and shortening the signal paths between functions of different dies that reduce energy consumption from signal transferring.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 March 21, 2026
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