-DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group II, (claims 17-20), in the reply filed on
02/23/2026 is acknowledged. NEW claims 21-29 are directed to a non-elected invention, including some limitations such as “…depositing a first conductive layer in the first opening in the second region and over the first sacrificial gate layer in the first region… …removing the first conductive layer, the dielectric layer, the second conductive layer formed in the first region; removing the first sacrificial gate layer to form a second opening in the first region…” so they are withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “…forming a fin over a substrate, wherein the fin is disposed in a first region, a second region, and a border region disposed between the first and second regions”, in claim 17 and “…depositing a first conductive layer in the first opening in the second region and over the first sacrificial gate layer in the first region… …removing the first sacrificial gate layer to form a second opening in the first region…” in claim 21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim 20 and 30-36 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, fails to adequately describe the combined process of claims 17 and 20. The disclosure of figs. 15A-18B and claim 20 requires the recessing of the fin in the third region, including a metal layer in the recessing followed by the formation of the third sacrificial gate layer, and then claim 17 requires the removal of the third sacrificial gate followed by the formation of the MIM structure. This would result in a capacitor structure where the MIM directly disposed on the metal layer, which is not described in the specification and creates a lack a written description issue.
Applicant is required to recite within claim 20 the deposition of dielectric layer 80 before the formation of the third sacrificial gate layer in order to overcome the issue raised above.
NEW claims 30-36 includes a new matter, figs. 15a-d, 16a-b, 17a-b, none of the figures shows "the first conductive layer extends over the isolation region”.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230378167 A1) in view of Doyle et al. (US 20080237675 A1, hereinafter Doyle).
Re: Independent Claim 17, Lee discloses a method, comprising:
forming a fin (fin-12 a top portion of substrate 12 in [0003], Fig. 1) over a substrate (12), wherein the fin (fin-12) is disposed in a first region (18 in [0019], Fig. 1), a second region (16 in [0019], Fig. 1), and a border region (14 in [0019], Fig. 1) disposed between (as the device is a 3-dimensional structure, the basic structure having 14-16-18 repeated at least two times let the region 14 in the middle of 16 and 18, Fig. 1-annotated) the first (18) and second (16) regions;
forming a first sacrificial gate layer (46 included in 18 and removed in a following step in [0022], Fig. 2) over a first portion of the fin (fin-12) located in the first region (18), a second sacrificial gate layer (46 included in 16 and removed in a following step in [0022], Fig. 2) over a second portion of the fin (fin-12) located in the second region (16), and a third sacrificial gate layer (46 included in 14 and removed in a following step in [0022], Fig. 2) over a third portion of the fin (fin-12) located in the border region (14);
removing the third sacrificial gate layer (46 included in 14) to create an opening (46 is removed and layers 44 and 132 are formed in the opening, Fig. 3);
removing the first (46 included in 18) and second (46 included in 16) sacrificial gate layers to form openings (46 in 16 and 18 is removed and gates 134,132,318,140,142 are formed in the opening in [0026], Fig. 3) in the first (18) and second (16) regions; and
depositing gate electrodes (gates 134,132,318,140,142 are formed in the opening in [0026], Fig. 3) in the openings in the first (18) and second (16) regions.
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Lee’s Figure 1-Annotated.
Lee does not expressly disclose forming a metal-insulator-metal (MIM) structure in the opening, wherein top surfaces of the gate electrodes and a top surface of the MIM structure are substantially co-planar.
However, in the same semiconductor device manufacturing field of endeavor, Doyle discloses forming a metal-insulator-metal (MIM) structure (810-910-1010 in [0033], Figs. 7-11) in the opening (710 Fig. 7), wherein top surfaces of the gate electrodes (245 gate electrode in [0026], Fig. 11) and a top surface of the MIM structure (810-910-1010) are substantially co-planar (Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Doyle’s method of forming a metal-insulator-metal (MIM) structure in the opening, wherein top surfaces of the gate electrodes and a top surface of the MIM structure are substantially co-planar to Lee’s method to increases the capacitance area of the capacitor ([0013], Doyle).
Re: Claim 18, Lee modified by Doyle discloses the method of claim 17, wherein forming the MIM structure (810-910-1010, Doyle) comprises depositing a first conductive layer (810, Doyle) in the opening, depositing a dielectric layer (910, Doyle) on the first conductive layer (810, Doyle), and depositing a second conductive layer (1010, Doyle) on the dielectric layer (910, Doyle).
Re: Claim 19, Lee modified by Doyle discloses the method of claim 18, wherein forming the MIM structure (810-910-1010, Doyle) further comprises removing portions (removing portions of 810 in [0033], Fig. 11, Doyle) of the first conductive layer (810, Doyle) and depositing a dielectric material (910, Doyle) to surround vertical sides (Fig. 11, Doyle) of the second conductive layer (1010, Doyle).
Claim(s) 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee in view of Doyle and further in view of Pidaparthi et al. (US 20230246027 A1, hereinafter Pidaparthi).
Re: Claim 20, Lee modified by Doyle discloses the method of claim 17,
Lee modified by Doyle does not expressly disclose further comprising recessing the third portion of the fin and depositing a third conductive layer on the recessed third portion of the fin prior to forming the third sacrificial gate layer.
However, in the same semiconductor device manufacturing field of endeavor, Pidaparthi discloses further comprising recessing (removing the top portion of fin 324, Fig. 3L-M) the third portion (the top portion of fin 324, Fig. 3M) of the fin (324) and depositing a third conductive layer (depositing a source metal layer 340 on the fin 324, in [0045], Fig. 3N) on the recessed (Fig. 3L-N) third portion of the fin (324).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Pidaparthi’s method of further comprising recessing the third portion of the fin and depositing a third conductive layer on the recessed third portion of the fin to the combination of Lee and Doyle to obtain further comprising recessing the third portion of the fin and depositing a third conductive layer on the recessed third portion of the fin prior to forming the third sacrificial gate layer to reduce the electrical conductivity of the fin tips and the area laterally adjacent the fin tips, thereby reducing their electrical activity or making them electrically inactive, resulting in many advantages ([0053], Pidaparthi).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Denorme et al. (US 20160343720 A1) teaches “METHOD FOR PRODUCING ONE-TIME-PROGRAMMABLE MEMORY CELLS AND CORRESPONDING INTEGRATED CIRCUIT”. This document is related to an integrated circuit including a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.
Booth et al. (US 20110291166 A1) teaches “INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR”. This document is related to a method of forming an integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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