Prosecution Insights
Last updated: August 18, 2026
Application No. 18/486,726

SYSTEMS AND METHODS FOR DIGITAL LITHOGRAPHY SCAN SEQUENCING

Final Rejection §102
Filed
Oct 13, 2023
Priority
Sep 01, 2023 — provisional 63/536,198
Examiner
PERSAUD, DEORAM
Art Unit
2882
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
6 (Final)
77%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
583 granted / 759 resolved
+8.8% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
26 currently pending
Career history
799
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
31.5%
-8.5% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 759 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Valverde-Paniagua et al. [US 2021/0216023 A1]. Regarding claims 1, 13 and 17, Valverde-Paniagua et al. discloses a digital lithography system (Figs. 1A and 1B) comprising: a stage (130) configured to support a substrate (140); a bridge (162) disposed above the stage (140); and a first lithographic processing unit (165) coupled to the bridge (162), comprising: an optical system (210) comprising one or more reduction optics and configured to transmit optical signals along a shared optical path via the one or more reduction optics both to and from the substrate and the first lithographic processing unit, wherein the shared optical path extends through the one or more reduction optics (paragraph [0033], see also Figs. 2A and 2B); a scanning unit (Figs. 2A and 2B) comprising an image sensor (208), the image sensor configured to capture images of the substrate via at least one reduction optic of the one or more reduction optics along the shared optical path (paragraph [0024] teaches the sensors are coupled the imaging apparatus to capture the reflection of the focus lasers off the substrate surface), wherein the scanning unit is configured to determine, based on the captured images, surface data indicative of positions of features on a surface of the substrate, wherein the images are captured via the at least one reduction optic of the one or more reduction optics along the shared optical path prior to digital lithographic exposure performed with respect to the substrate (paragraphs [0040]-[0042] teaches the channel of the image projection apparatus includes one or more spatial light modulators, an alignment and inspection system including a focus sensor and a camera, and a plurality of projection optics); and a lithographic exposure unit (164) configured to perform, based on the surface data determined using the captured images, digital lithographic exposure of the substrate via the at least one reduction optic of the one or more reduction optics along the shared optical path (as shown in Fig. 5, see also paragraph [0047] teaches autofocusing on a substrate during a substrate patterning operation). Regarding claims 2, 11, 12, 14 and 19, Valverde-Paniagua et al. discloses further comprising: a controller (192, see also paragraphs [0034]-[0035]) configured to: cause the first lithographic processing unit to capture the images of the substrate at a first time during a measurement operation; determine remedial updates for a lithographic exposure pattern based on the captured images; and cause the first lithographic processing unit to perform the digital lithographic exposure of the substrate according to the lithographic exposure pattern as adjusted by the remedial updates at a second time during an exposure operation (as shown in Fig. 5, see also paragraph [0047]), further comprising: a chuck to clamp the substrate to the stage prior to the measurement operation or the exposure operation, wherein the clamp of the substrate to the stage is not released until after the exposure operation, wherein the chuck comprises an electrostatic chuck (paragraphs [0036]-[0038]). Regarding claims 3, 16 and 20, Valverde-Paniagua et al. discloses further comprising: a plurality of adjacent processing regions spanning a surface profile of the substrate, wherein the first lithographic processing unit is positioned to operate on a first processing region of the plurality of adjacent processing regions; and one or more additional lithographic processing units, each of the one or more additional lithographic processing units is positioned to operate on an additional processing region of the plurality of adjacent processing regions at a same time that the first lithographic processing unit is to operate on the first processing region (as shown in Figs. 1-4). Regarding claim 4, Valverde-Paniagua et al. discloses wherein the lithographic exposure unit comprises an actinic light source and a spatial light modulator, and scanning unit comprises an image sensor (as shown in Figs. 2A and 2B). Regarding claims 5-7, Valverde-Paniagua et al. discloses wherein the first lithographic processing unit further comprises a first brightfield light source, wherein the scanning unit further comprises a second brightfield light source or a darkfield light source, wherein the scanning unit further comprises a second brightfield light source and a darkfield light source (paragraph [0040]). Regarding claim 8, Valverde-Paniagua et al. discloses wherein the optical system, the scanning unit, and the lithographic exposure unit transmit and receive optical signals along a common longitudinal axis of the first lithographic processing unit (as shown in Figs. 2A and 2B). Regarding claim 9, Valverde-Paniagua et al. discloses wherein the optical system comprises reduction optics configured to reduce an image of a lithographic mask pattern onto a surface of the substrate (as shown in Figs. 2A and 2B). Regarding claims 10, 15 and 18, Valverde-Paniagua et al. discloses wherein the stage is configured to support the substrate at a first region and is further configured to support a second substrate at a second region, the digital lithography system further comprising: a second lithographic processing unit coupled to the bridge, comprising: a second scanning unit; a second lithographic exposure unit; and a second optical system shared by the second scanning unit and the second lithographic exposure unit; wherein the second scanning unit is to use the second optical system to capture images of the second substrate during a measurement operation, and wherein the second lithographic exposure unit is to use the second optical system to perform digital lithographic exposure of the second substrate using the second optical system during an exposure operation, further comprising: a robotic system to move the first substrate off of the second region of the stage, to move the second substrate from the first region of the stage to the second region of the stage, and to move the third substrate to the first region of the stage; wherein the controller is further to: determine remedial updates for a lithographic exposure pattern for the second substrate based on the captured images; cause the first scanning unit to capture images of the third substrate at a second time; and cause the first lithographic exposure unit to perform digital lithographic exposure of the second substrate according to the lithographic exposure pattern as adjusted by the remedial updates at the second time (as shown in Figs. 1-5). Response to Arguments Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEORAM PERSAUD whose telephone number is (571)270-5476. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Minh-Toan Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DEORAM PERSAUD/Primary Examiner, Art Unit 2882
Read full office action

Prosecution Timeline

Show 14 earlier events
Mar 04, 2026
Examiner Interview Summary
Mar 09, 2026
Request for Continued Examination
Mar 17, 2026
Response after Non-Final Action
Apr 01, 2026
Non-Final Rejection mailed — §102
Jun 05, 2026
Applicant Interview (Telephonic)
Jun 05, 2026
Examiner Interview Summary
Jun 23, 2026
Response Filed
Jul 23, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+11.8%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 759 resolved cases by this examiner. Grant probability derived from career allowance rate.

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